Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

A Circuit-Based Neural Network with Hybrid Learning of Backpropagation and Random Weight Change Algorithms.

A hybrid learning method of a software-based backpropagation learning and a hardware-based RWC learning is proposed for the development of circuit-based neural networks. The backpropagation is known as one of the most efficient learning algorithms. A weak point is that its hardware implementation is extremely difficult. The RWC algorithm, which is very easy to implement with respect to its hardware circuits, takes too many iterations for learning. The proposed learning algorithm is a hybrid one of these two. The main learning is performed with a software version of the BP algorithm, firstly, and then, learned weights are transplanted on a hardware version of a neural circuit. At the time of the weight transplantation, a significant amount of output error would occur due to the characteristic difference between the software and the hardware. In the proposed method, such error is reduced via a complementary learning of the RWC algorithm, which is implemented in a simple hardware. The usefulness of the proposed hybrid learning system is verified via simulations upon several classical learning problems

Fully CMOS Memristor Based Chaotic Circuit

This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

First order devices, hybrid memristors, and the frontiers of nonlinear circuit theory

Several devices exhibiting memory effects have shown up in nonlinear circuit theory in recent years. Among others, these circuit elements include Chua's memristors, as well as memcapacitors and meminductors. These and other related devices seem to be beyond the, say, classical scope of circuit theory, which is formulated in terms of resistors, capacitors, inductors, and voltage and current sources. We explore in this paper the potential extent of nonlinear circuit theory by classifying such mem-devices in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. Within this framework, the frontier of first order circuit theory is defined by so-called hybrid memristors, which are proposed here to accommodate a characteristic relating all four fundamental circuit variables. Devices with differential order two and mem-systems are discussed in less detail. We allow for fully nonlinear characteristics in all circuit elements, arriving at a rather exhaustive taxonomy of C^1-devices. Additionally, we extend the notion of a topologically degenerate configuration to circuits with memcapacitors, meminductors and all types of memristors, and characterize the differential-algebraic index of nodal models of such circuits.Comment: Published in 2013. Journal reference included as a footnote in the first pag