805 research outputs found
Reliable Modeling of Ideal Generic Memristors via State-Space Transformation
The paper refers to problems of modeling and computer simulation of generic memristors caused by the so-called window functions, namely the stick effect, nonconvergence, and finding fundamentally incorrect solutions. A profoundly different modeling approach is proposed, which is mathematically equivalent to window-based modeling. However, due to its numerical stability, it definitely smoothes the above problems away
The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor
In 2008, researchers at HP Labs published a paper in {\it Nature} reporting
the realisation of a new basic circuit element that completes the missing link
between charge and flux-linkage, which was postulated by Leon Chua in 1971. The
HP memristor is based on a nanometer scale TiO thin-film, containing a
doped region and an undoped region. Further to proposed applications of
memristors in artificial biological systems and nonvolatile RAM (NVRAM), they
also enable reconfigurable nanoelectronics. Moreover, memristors provide new
paradigms in application specific integrated circuits (ASICs) and field
programmable gate arrays (FPGAs). A significant reduction in area with an
unprecedented memory capacity and device density are the potential advantages
of memristors for Integrated Circuits (ICs). This work reviews the memristor
and provides mathematical and SPICE models for memristors. Insight into the
memristor device is given via recalling the quasi-static expansion of Maxwell's
equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings
of Royal Society
Fully CMOS Memristor Based Chaotic Circuit
This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications
Application of Memristors in Microwave Passive Circuits
The recent implementation of the fourth fundamental electric circuit element, the memristor, opened new vistas in many fields of engineering applications. In this paper, we explore several RF/microwave passive circuits that might benefit from the memristor salient characteristics. We consider a power divider, coupled resonator bandpass filters, and a low-reflection quasi-Gaussian lowpass filter with lossy elements. We utilize memristors as configurable linear resistors and we propose memristor-based bandpass filters that feature suppression of parasitic frequency pass bands and widening of the desired rejection band. The simulations are performed in the time domain, using LTspice, and the RF/microwave circuits under consideration are modeled by ideal elements available in LTspice
Spice model of current polarity-dependent piecewise linear window function for memristors
Memristor and memristive systems are nonlinear systems. It is important to model them accurately. There are different memristor models and most of the models make use of window functions. In literature, there are various window functions. Recently, a piecewise linear (PWL) window function is used to model a memristor and memristive systems. Such a memristor with a PWL window function lacks a SPICE model. Also, in literature, there is current polarity dependent window functions proposed for memristors to model polarity dependent drift speed within the thin-film memristors. In this study, an alternative current-polarity dependent PWL window function is suggested to model a memristor, a different PWL function one for each current polarity is used, its SPICE model is made in LTSpice and also its simulation results are given. Such a model can be used to model the polarity dependent drift speed within the thin-film memristors. © 2020, Gazi Universitesi. All rights reserved
SPICE model of memristive devices with threshold
Although memristive devices with threshold voltages are the norm rather than
the exception in experimentally realizable systems, their SPICE programming is
not yet common. Here, we show how to implement such systems in the SPICE
environment. Specifically, we present SPICE models of a popular
voltage-controlled memristive system specified by five different parameters for
PSPICE and NGSPICE circuit simulators. We expect this implementation to find
widespread use in circuits design and testing
An On-chip Trainable and Clock-less Spiking Neural Network with 1R Memristive Synapses
Spiking neural networks (SNNs) are being explored in an attempt to mimic
brain's capability to learn and recognize at low power. Crossbar architecture
with highly scalable Resistive RAM or RRAM array serving as synaptic weights
and neuronal drivers in the periphery is an attractive option for SNN.
Recognition (akin to reading the synaptic weight) requires small amplitude bias
applied across the RRAM to minimize conductance change. Learning (akin to
writing or updating the synaptic weight) requires large amplitude bias pulses
to produce a conductance change. The contradictory bias amplitude requirement
to perform reading and writing simultaneously and asynchronously, akin to
biology, is a major challenge. Solutions suggested in the literature rely on
time-division-multiplexing of read and write operations based on clocks, or
approximations ignoring the reading when coincidental with writing. In this
work, we overcome this challenge and present a clock-less approach wherein
reading and writing are performed in different frequency domains. This enables
learning and recognition simultaneously on an SNN. We validate our scheme in
SPICE circuit simulator by translating a two-layered feed-forward Iris
classifying SNN to demonstrate software-equivalent performance. The system
performance is not adversely affected by a voltage dependence of conductance in
realistic RRAMs, despite departing from linearity. Overall, our approach
enables direct implementation of biological SNN algorithms in hardware
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