Power efficient job scheduling by predicting the impact of processor manufacturing variability

Modern CPUs suffer from performance and power consumption variability due to the manufacturing process. As a result, systems that do not consider such variability caused by manufacturing issues lead to performance degradations and wasted power. In order to avoid such negative impact, users and system administrators must actively counteract any manufacturing variability. In this work we show that parallel systems benefit from taking into account the consequences of manufacturing variability when making scheduling decisions at the job scheduler level. We also show that it is possible to predict the impact of this variability on specific applications by using variability-aware power prediction models. Based on these power models, we propose two job scheduling policies that consider the effects of manufacturing variability for each application and that ensure that power consumption stays under a system-wide power budget. We evaluate our policies under different power budgets and traffic scenarios, consisting of both single- and multi-node parallel applications, utilizing up to 4096 cores in total. We demonstrate that they decrease job turnaround time, compared to contemporary scheduling policies used on production clusters, up to 31% while saving up to 5.5% energy.Postprint (author's final draft

Energy Efficiency in the ICT - Profiling Power Consumption in Desktop Computer Systems

Energy awareness in the ICT has become an important issue. Focusing on software, recent work suggested the existence of a relationship between power consumption, software configuration and usage patterns in computer systems. The aim of this work was collecting and analysing power consumption data of general-purpose computer systems, simulating common usage scenarios, in order to extract a power consumption profile for each scenario. We selected two desktop systems of different generations as test machines. Meanwhile, we developed 11 usage scenarios, and conducted several test runs of them, collecting power consumption data by means of a power meter. Our analysis resulted in an estimation of a power consumption value for each scenario and software application used, obtaining that each single scenario introduced an overhead from 2 to 11 Watts, which corresponds to a percentage increase that can reach up to 20% on recent and more powerful systems. We determined that software and its usage patterns impact consistently on the power consumption of computer systems. Further work will be devoted to evaluate how power consumption is affected by the usage of specific system resource

Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications. In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication (gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric--static and dynamic scheduling strategies that carefully tune and distribute the operation's micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency

DyPS: Dynamic Processor Switching for Energy-Aware Video Decoding on Multi-core SoCs

In addition to General Purpose Processors (GPP), Multicore SoCs equipping modern mobile devices contain specialized Digital Signal Processor designed with the aim to provide better performance and low energy consumption properties. However, the experimental measurements we have achieved revealed that system overhead, in case of DSP video decoding, causes drastic performances drop and energy efficiency as compared to the GPP decoding. This paper describes DyPS, a new approach for energy-aware processor switching (GPP or DSP) according to the video quality . We show the pertinence of our solution in the context of adaptive video decoding and describe an implementation on an embedded Linux operating system with the help of the GStreamer framework. A simple case study showed that DyPS achieves 30% energy saving while sustaining the decoding performanc

MOSDEN: A Scalable Mobile Collaborative Platform for Opportunistic Sensing Applications

Mobile smartphones along with embedded sensors have become an efficient enabler for various mobile applications including opportunistic sensing. The hi-tech advances in smartphones are opening up a world of possibilities. This paper proposes a mobile collaborative platform called MOSDEN that enables and supports opportunistic sensing at run time. MOSDEN captures and shares sensor data across multiple apps, smartphones and users. MOSDEN supports the emerging trend of separating sensors from application-specific processing, storing and sharing. MOSDEN promotes reuse and re-purposing of sensor data hence reducing the efforts in developing novel opportunistic sensing applications. MOSDEN has been implemented on Android-based smartphones and tablets. Experimental evaluations validate the scalability and energy efficiency of MOSDEN and its suitability towards real world applications. The results of evaluation and lessons learned are presented and discussed in this paper.Comment: Accepted to be published in Transactions on Collaborative Computing, 2014. arXiv admin note: substantial text overlap with arXiv:1310.405

An Algorithm for Network and Data-aware Placement of Multi-Tier Applications in Cloud Data Centers

Today's Cloud applications are dominated by composite applications comprising multiple computing and data components with strong communication correlations among them. Although Cloud providers are deploying large number of computing and storage devices to address the ever increasing demand for computing and storage resources, network resource demands are emerging as one of the key areas of performance bottleneck. This paper addresses network-aware placement of virtual components (computing and data) of multi-tier applications in data centers and formally defines the placement as an optimization problem. The simultaneous placement of Virtual Machines and data blocks aims at reducing the network overhead of the data center network infrastructure. A greedy heuristic is proposed for the on-demand application components placement that localizes network traffic in the data center interconnect. Such optimization helps reducing communication overhead in upper layer network switches that will eventually reduce the overall traffic volume across the data center. This, in turn, will help reducing packet transmission delay, increasing network performance, and minimizing the energy consumption of network components. Experimental results demonstrate performance superiority of the proposed algorithm over other approaches where it outperforms the state-of-the-art network-aware application placement algorithm across all performance metrics by reducing the average network cost up to 67% and network usage at core switches up to 84%, as well as increasing the average number of application deployments up to 18%.Comment: Submitted for publication consideration for the Journal of Network and Computer Applications (JNCA). Total page: 28. Number of figures: 15 figure

Predicting topology propagation messages in mobile ad hoc networks: The value of history

This research was funded by the Spanish Government under contracts TIN2016-77836-C2-1-R,TIN2016-77836-C2-2-R, and DPI2016-77415-R, and by the Generalitat de Catalunya as Consolidated ResearchGroups 2017-SGR-688 and 2017-SGR-990.The mobile ad hoc communication in highly dynamic scenarios, like urban evacuations or search-and-rescue processes, plays a key role in coordinating the activities performed by the participants. Particularly, counting on message routing enhances the communication capability among these actors. Given the high dynamism of these networks and their low bandwidth, having mechanisms to predict the network topology offers several potential advantages; e.g., to reduce the number of topology propagation messages delivered through the network, the consumption of resources in the nodes and the amount of redundant retransmissions. Most strategies reported in the literature to perform these predictions are limited to support high mobility, consume a large amount of resources or require training. In order to contribute towards addressing that challenge, this paper presents a history-based predictor (HBP), which is a prediction strategy based on the assumption that some topological changes in these networks have happened before in the past, therefore, the predictor can take advantage of these patterns following a simple and low-cost approach. The article extends a previous proposal of the authors and evaluates its impact in highly mobile scenarios through the implementation of a real predictor for the optimized link state routing (OLSR) protocol. The use of this predictor, named OLSR-HBP, shows a reduction of 40–55% of topology propagation messages compared to the regular OLSR protocol. Moreover, the use of this predictor has a low cost in terms of CPU and memory consumption, and it can also be used with other routing protocols.Peer ReviewedPostprint (published version