Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals

Turbo-Detected Unequal Protection MPEG-4 Wireless Video Telephony using Multi-Level Coding, Trellis Coded Modulation and Space-Time Trellis Coding

Most multimedia source signals are capable of tolerating lossy, rather than lossless delivery to the human eye, ear and other human sensors. The corresponding lossy and preferably low-delay multimedia source codecs however exhibit unequal error sensitivity, which is not the case for Shannon’s ideal entropy codec. This paper proposes a jointly optimised turbo transceiver design capable of providing unequal error protection for MPEG-4 coding aided wireless video telephony. The transceiver investigated consists of space-time trellis coding (STTC) invoked for the sake of mitigating the effects of fading, in addition to bandwidth efficient trellis coded modulation or bit-interleaved coded modulation, combined with a multi-level coding scheme employing either two different-rate non-systematic convolutional codes (NSCs) or two recursive systematic convolutional codes for yielding a twin-class unequal-protection. A single-class protection based benchmark scheme combining STTC and NSC is used for comparison with the unequal-protection scheme advocated. The video performance of the various schemes is evaluated when communicating over uncorrelated Rayleigh fading channels. It was found that the proposed scheme requires about 2.8 dBs lower transmit power than the benchmark scheme in the context of the MPEG-4 videophone transceiver at a similar decoding complexity

Hybrid ARQ with parallel and serial concatenated convolutional codes for next generation wireless communications

This research focuses on evaluating the currently used FEC encoding-decoding schemes and improving the performance of error control systems by incorporating these schemes in a hybrid FEC-ARQ environment. Beginning with an overview of wireless communications and the various ARQ protocols, the thesis provides an in-depth explanation of convolutional encoding and Viterbi decoding, turbo (PCCC) and serial concatenated convolutional (SCCC) encoding with their respective MAP decoding strategies.;A type-II hybrid ARQ scheme with SCCCs is proposed for the first time and is a major contribution of this thesis. A vast improvement is seen in the BER performance of the successive individual FEC schemes discussed above. Also, very high throughputs can be achieved when these schemes are incorporated in an adaptive type-II hybrid ARQ system.;Finally, the thesis discusses the equivalence of the PCCCs and the SCCCs and proposes a technique to generate a hybrid code using both schemes

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications