Accumulator-free Hough Transform for Sequence Collinear Points

The perception, localization, and navigation of its environment are essential for autonomous mobile robots and vehicles. For that reason, a 2D Laser rangefinder sensor is used popularly in mobile robot applications to measure the origin of the robot to its surrounding objects. The measurement data generated by the sensor is transmitted to the controller, where the data is processed by one or multiple suitable algorithms in several steps to extract the desired information. Universal Hough Transform (UHT) is one of the appropriate and popular algorithms to extract the primitive geometry such as straight line, which later will be used in the further step of data processing. However, the UHT has high computational complexity and requires the so-called accumulator array, which is less suitable for real-time applications where a high speed and low complexity computation is highly demanded. In this study, an Accumulator-free Hough Transform (AfHT) is proposed to reduce the computational complexity and eliminate the need for the accumulator array. The proposed algorithm is validated using the measurement data from a 2D laser scanner and compared to the standard Hough Transform. As a result, the extracted value of AfHT shows a good agreement with that of UHT but with a significant reduction in the complexity of the computation and the need for computer memory

Implementation of a real time Hough transform using FPGA technology

This thesis is concerned with the modelling, design and implementation of efficient architectures for performing the Hough Transform (HT) on mega-pixel resolution real-time images using Field Programmable Gate Array (FPGA) technology. Although the HT has been around for many years and a number of algorithms have been developed it still remains a significant bottleneck in many image processing applications. Even though, the basic idea of the HT is to locate curves in an image that can be parameterized: e.g. straight lines, polynomials or circles, in a suitable parameter space, the research presented in this thesis will focus only on location of straight lines on binary images. The HT algorithm uses an accumulator array (accumulator bins) to detect the existence of a straight line on an image. As the image needs to be binarized, a novel generic synchronization circuit for windowing operations was designed to perform edge detection. An edge detection method of special interest, the canny method, is used and the design and implementation of it in hardware is achieved in this thesis. As each image pixel can be implemented independently, parallel processing can be performed. However, the main disadvantage of the HT is the large storage and computational requirements. This thesis presents new and state-of-the-art hardware implementations for the minimization of the computational cost, using the Hybrid-Logarithmic Number System (Hybrid-LNS) for calculating the HT for fixed bit-width architectures. It is shown that using the Hybrid-LNS the computational cost is minimized, while the precision of the HT algorithm is maintained. Advances in FPGA technology now make it possible to implement functions as the HT in reconfigurable fabrics. Methods for storing large arrays on FPGA’s are presented, where data from a 1024 x 1024 pixel camera at a rate of up to 25 frames per second are processed