165,734 research outputs found
Coherent control of microwave pulse storage in superconducting circuits
Coherent pulse control for quantum memory is viable in the optical domain but
nascent in microwave quantum circuits. We show how to realize coherent storage
and on-demand pulse retrieval entirely within a superconducting circuit by
exploiting and extending existing electromagnetically induced transparency
technology in superconducting quantum circuits. Our scheme employs a linear
array of superconducting artificial atoms coupled to a microwave transmission
line.Comment: 13 pages, 4 figures and some supplementary materia
Design of Adiabatic MTJ-CMOS Hybrid Circuits
Low-power designs are a necessity with the increasing demand of portable
devices which are battery operated. In many of such devices the operational
speed is not as important as battery life. Logic-in-memory structures using
nano-devices and adiabatic designs are two methods to reduce the static and
dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an
emerging technology which has many advantages when used in logic-in-memory
structures in conjunction with CMOS. In this paper, we introduce a novel
adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR
and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm
CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits.
The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower
power consumtion compared to the previous MTJ/CMOS full adder
Beyond Moore's technologies: operation principles of a superconductor alternative
The predictions of Moore's law are considered by experts to be valid until
2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency
is one of the major challenges in high-performance computing that should be
answered. Superconductor digital technology is a promising post-Moore's
alternative for the development of supercomputers. In this paper, we consider
operation principles of an energy-efficient superconductor logic and memory
circuits with a short retrospective review of their evolution. We analyze their
shortcomings in respect to computer circuits design. Possible ways of further
research are outlined.Comment: OPEN ACCES
NanoMagnet Logic: an Architectural Viewpoint
Among the possible implementation of Field- Coupled devices NanoMagnet Logic is attractive for its low power consumption and the possibility to combine memory and logic in the same device. However, the nature of these technologies is so different from CMOS transistors that the implications on the circuit architecture must be taken carefully into account. In this work we analyze the most important issues related to the design of complex circuits using this technology. We discuss how they influence the architectural level. We propose detailed solutions to solve these problems and to improve the overall performance. As a result of this analysis the type of circuits and applications that constitute the best target for this technology are identified. The analysis is performed on NanoMagnet Logic but the results can be applied to any QCA technolog
Packaging of a large capacity magnetic bubble domain spacecraft recorder
A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply
Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells
The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling down of the technology. In particular, even small variations of parasitic capacitances in CMOS devices are expected to become an additional source of faulty behaviors in future technologies. This paper analyzes and compares the effect of parasitic capacitance variations in a SRAM memory circuit realized with 65 nm and 32 nm predictive technology model
Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors
Memory circuit elements, namely memristive, memcapacitive and meminductive systems, are gaining considerable attention due to their ubiquity and use in diverse areas of science and technology. Their modeling within the most widely used environment, SPICE, is thus critical to make substantial progress in the design and analysis of complex circuits. Here, we present a collection of models of different memory circuit elements and provide a methodology for their accurate and reliable modeling in the SPICE environment. We also provide codes of these models written in the most popular SPICE versions (PSpice, LTspice, HSPICE) for the benefit of the reader. We expect this to be of great value to the growing community of scientists interested in the wide range of applications of memory circuit elements
Design of a Superconducting Multiflux Non-Destructive Readout Memory Unit
Due to low power consumption and high-speed performance, superconductor
circuit technology has emerged as an attractive and compelling post-CMOS
technology candidate. However, the design of dense memory circuits presents a
significant challenge, especially for tasks that demand substantial memory
resources. While superconductor memory cells offer impressive speed, their
limited density is the primary yet-to-be-solved challenge. This study tackles
this challenge head-on by introducing a novel design for a Non-Destructive
Readout (NDRO) memory unit with single or multi-fluxon storage capabilities
within the same circuit architecture. Notably, single storage demonstrates a
critical margin exceeding 20\%, and multi-fluxon storage demonstrates 64\%,
ensuring reliable and robust operation even in the face of process variations.
These memory units exhibit high clock frequencies of 10GHz. The proposed
circuits offer compelling characteristics, including rapid data propagation and
minimal data refreshment requirements, while effectively addressing the density
concerns associated with superconductor memory, doubling the memory capacity
while maintaining the high throughput speed.Comment: 6 pages, 11 figure
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