325 research outputs found
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low-power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system including error control, system decomposition, communication and MAC protocols, and low-power short range networks
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Low Power system Design techniques for mobile computers
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, sys tem decomposition, communication and MAC protocols, and low power short range net works
Learning from minimally labeled data with accelerated convolutional neural networks
The main objective of an Artificial Vision Algorithm is to design a mapping function that takes an image as an input and correctly classifies it into one of the user-determined categories. There are several important properties to be satisfied by the mapping function for visual understanding. First, the function should produce good representations of the visual world, which will be able to recognize images independently of pose, scale and illumination. Furthermore, the designed artificial vision system has to learn these representations by itself. Recent studies on Convolutional Neural Networks (ConvNets) produced promising advancements in visual understanding. These networks attain significant performance upgrades by relying on hierarchical structures inspired by biological vision systems. In my research, I work mainly in two areas: 1) how ConvNets can be programmed to learn the optimal mapping function using the minimum amount of labeled data, and 2) how these networks can be accelerated for practical purposes. In this work, algorithms that learn from unlabeled data are studied. A new framework that exploits unlabeled data is proposed. The proposed framework obtains state-of-the-art performance results in different tasks.
Furthermore, this study presents an optimized streaming method for ConvNetsâ hardware accelerator on an embedded platform. It is tested on object classification and detection applications using ConvNets. Experimental results indicate high computational efficiency, and significant performance upgrades over all other existing platforms
Accelerating Fully Connected Neural Network on Optical Network-on-Chip (ONoC)
Fully Connected Neural Network (FCNN) is a class of Artificial Neural
Networks widely used in computer science and engineering, whereas the training
process can take a long time with large datasets in existing many-core systems.
Optical Network-on-Chip (ONoC), an emerging chip-scale optical interconnection
technology, has great potential to accelerate the training of FCNN with low
transmission delay, low power consumption, and high throughput. However,
existing methods based on Electrical Network-on-Chip (ENoC) cannot fit in ONoC
because of the unique properties of ONoC. In this paper, we propose a
fine-grained parallel computing model for accelerating FCNN training on ONoC
and derive the optimal number of cores for each execution stage with the
objective of minimizing the total amount of time to complete one epoch of FCNN
training. To allocate the optimal number of cores for each execution stage, we
present three mapping strategies and compare their advantages and disadvantages
in terms of hotspot level, memory requirement, and state transitions.
Simulation results show that the average prediction error for the optimal
number of cores in NN benchmarks is within 2.3%. We further carry out extensive
simulations which demonstrate that FCNN training time can be reduced by 22.28%
and 4.91% on average using our proposed scheme, compared with traditional
parallel computing methods that either allocate a fixed number of cores or
allocate as many cores as possible, respectively. Compared with ENoC,
simulation results show that under batch sizes of 64 and 128, on average ONoC
can achieve 21.02% and 12.95% on reducing training time with 47.85% and 39.27%
on saving energy, respectively.Comment: 14 pages, 10 figures. This paper is under the second review of IEEE
Transactions of Computer
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