1,755 research outputs found
Optimum non linear binary image restoration through linear grey-scale operations
Non-linear image processing operators give excellent results in a number of image processing tasks such as restoration and object recognition. However they are frequently excluded from use in solutions because the system designer does not wish to introduce additional hardware or algorithms and because their design can appear to be ad hoc. In practice the median filter is often used though it is rarely optimal. This paper explains how various non-linear image processing operators may be implemented on a basic linear image processing system using only convolution and thresholding operations. The paper is aimed at image processing system developers wishing to include some non-linear processing operators without introducing additional system capabilities such as extra hardware components or software toolboxes. It may also be of benefit to the interested reader wishing to learn more about non-linear operators and alternative methods of design and implementation. The non-linear tools include various components of mathematical morphology, median and weighted median operators and various order statistic filters. As well as describing novel algorithms for implementation within a linear system the paper also explains how the optimum filter parameters may be estimated for a given image processing task. This novel approach is based on the weight monotonic property and is a direct rather than iterated method
Digital implementation of the cellular sensor-computers
Two different kinds of cellular sensor-processor architectures are used nowadays in various
applications. The first is the traditional sensor-processor architecture, where the sensor and the
processor arrays are mapped into each other. The second is the foveal architecture, in which a
small active fovea is navigating in a large sensor array. This second architecture is introduced
and compared here. Both of these architectures can be implemented with analog and digital
processor arrays. The efficiency of the different implementation types, depending on the used
CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use
digital implementation rather than analog
A System On Chip Dedicated To Pipeline Neighborhood Processing For Mathematical Morphology
Also available at http://www.eurasip.org/Proceedings/Eusipco/Eusipco2008/papers/1569104317.pdfInternational audienceThis paper describes a system on chip for image processing. It is based on a pipe-line of neighborhood processors named SPoC and is controlled by a general purpose processor. Each SPoC are connected one to the other through a reconfigurable data path to get more adaptability and their structure exploits temporal and spatial parallelism to speed up computations and minimize memory transfers. Two applications, a motion detection algorithm and a licence plate extraction, are presented to show performances in terms of speed, embeddability and re-usability of the SoC. Comparisons with many architectures such as digital signal processors, workstations or embedded SIMD processors are made to benchmark the platform and prove the originality and the strength of our solution
Vision-Based Road Detection in Automotive Systems: A Real-Time Expectation-Driven Approach
The main aim of this work is the development of a vision-based road detection
system fast enough to cope with the difficult real-time constraints imposed by
moving vehicle applications. The hardware platform, a special-purpose massively
parallel system, has been chosen to minimize system production and operational
costs. This paper presents a novel approach to expectation-driven low-level
image segmentation, which can be mapped naturally onto mesh-connected massively
parallel SIMD architectures capable of handling hierarchical data structures.
The input image is assumed to contain a distorted version of a given template;
a multiresolution stretching process is used to reshape the original template
in accordance with the acquired image content, minimizing a potential function.
The distorted template is the process output.Comment: See http://www.jair.org/ for any accompanying file
Fast signal processing
ZvÄtĆĄujĂcĂ se mnoĆŸstvĂ dat v modernĂm zpracovĂĄnĂ obrazu vyĆŸaduje novĂœ postupy v psanĂ algoritmĆŻ. NejvÄtĆĄĂ pĆekĂĄĆŸkou pro ĂșspÄĆĄnĂ© zrychlenĂ algoritmu je paralelizace a nĂĄslednĂĄ optimalizace. Programy jako CUDA a OpenCL s modifikovanĂœm programovacĂm jazykem a rozhranĂm pomĂĄhajĂ s tĂmto problĂ©mem a otevĂrajĂ paralelnĂ zpracovĂĄnĂ ĆĄirĆĄĂmu okruhu lidĂ. V tĂ©to prĂĄci zabĂœvĂĄm zĂĄklady zpracovĂĄnĂ obrazu a tomu jak paralelizace algoritmĆŻ mĆŻĆŸe urychlit zpracovĂĄnĂ obrazu.An increasing amount of data in modern image processing requires a new approach in algorithms. The biggest obstacle for successful speed up of an algorithm is parallelization and subsequent optimization. Architectures like CUDA and OpenCL with modified programing languages and interfaces help to overcome this obstacle and bring parallel computing to a broader audience. In this paper I take a look at basics of image processing and how parallelization can speed up the algorithms in image processing.
Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C
Computer manipulation of images is generally defined as Digital Image Processing (DIP). DIP is used in variety of applications, including video surveillance, target recognition, and image enhancement. These applications are usually implemented in software but may use special purpose hardware for speed. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithms yield significant speedup in running times. In this thesis the image processing algorithms like median filter, basic morphological operators, convolution and edge detection algorithms are implemented on FPGA. A pipelined architecture of these algorithms is presented. The proposed architectures are capable of producing one output on every clock cycle. The hardware modeling was accomplished using Handel-C (DK2 environment). The algorithm was tested on standard image processing benchmarks and the results are compared with that obtained on software
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