Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering

Design and validation of key components for the readout electronics of future PET scanners

This thesis work discusses the design and validation of two circuit components used in the electronic readout of positron emission tomography (PET) scanners for biomedical applications: a constant fraction discriminator (CFD) and an integrated CMOS time to digital converter (TDC). The former is used in the read out of a double-head PET scanner already developed by the group of medical physics at INFN Pisa for non-invasive dose delivery monitoring in hadrontherapy. The goal of the work has been the optimization of the front-end PCB in terms of timing performances so as to reduce the dead time and resolution at system level. A new CFD board has been implemented and experimental results have shown a significant enhancement of the timing characteristics which have enabled performing in-beam PET data acquisition which is fundamental in hadrontherapy treatment. The design of an integrated CMOS TDC to be used for the time of flight measurement in a magnetic field-compatible PET block detector is the second topic of the thesis. The required time resolutions, linear behaviour as well as the communication with other readout elements have been taken into account in the definition of the circuit topology. Cadence and Verilog simulations have shown that a bin size of 100 ps can be obtained with the combination of a submicron technology (UMC 65 nm LLLVT) and a pipeline approach where a 10 bit systolic counter coupled to a 4 stage delay locked loop (DLL) are exploited. This translates into a nominal resolution of 29 ps. In addition, the use of a short DLL leads to a high linearity which is an issue in PET measurements. Despite lower resolutions are obtained in literature with different TDC topologies, achieving good performances in terms of both time resolution and linearity is not straightforward. The converter also features a real-time validation algorithm which is capable to reject noise inputs generated by the photodetector without impairing the acquisition capability of the system. A standard-cell unit has been also designed which is in charge of data buffering and serial communication with external readout boards. A 47 bit output word is provided by the semi-custom stage at a measurement rate which is selectable between 31.25 MHz and 62.5 MHz with a double hit resolution of 170 ns. An 8 channel prototype of 1.875 x 1.875 mm2 has been submitted in March 2013 in order to validate simulated data with experimental results