5,548 research outputs found
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
Accurate estimation of switching activity is very important in
digital circuits. In this paper we present a comparison between the evaluation
of the switching activity calculated using logic (Verilog) and electrical
(HSPICE) simulators. We also study how the variation on the delay model
(min, typ, max) and parasitic effects affect the number of transitions in the
circuit. Results show a variable and significant overestimation of this
measurement using logic simulators even when including postlayout effects.
Furthermore, we show the contribution of glitches to the overall switching
activity, giving that the treatment of glitches in conventional logic simulators
is the main cause of switching activity overestimation.Ministerio de Ciencia y TecnologĂa TIC 2000-1350Ministerio de Ciencia y TecnologĂa TIC 2002-228
Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"
Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 Âżm CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30
Ultra-Low-Power Superconductor Logic
We have developed a new superconducting digital technology, Reciprocal
Quantum Logic, that uses AC power carried on a transmission line, which also
serves as a clock. Using simple experiments we have demonstrated zero static
power dissipation, thermally limited dynamic power dissipation, high clock
stability, high operating margins and low BER. These features indicate that the
technology is scalable to far more complex circuits at a significant level of
integration. On the system level, Reciprocal Quantum Logic combines the high
speed and low-power signal levels of Single-Flux- Quantum signals with the
design methodology of CMOS, including low static power dissipation, low latency
combinational logic, and efficient device count.Comment: 7 pages, 5 figure
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