1,367 research outputs found

    Waiting times in queueing networks with a single shared server

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    We study a queueing network with a single shared server that serves the queues in a cyclic order. External customers arrive at the queues according to independent Poisson processes. After completing service, a customer either leaves the system or is routed to another queue. This model is very generic and finds many applications in computer systems, communication networks, manufacturing systems, and robotics. Special cases of the introduced network include well-known polling models, tandem queues, systems with a waiting room, multi-stage models with parallel queues, and many others. A complicating factor of this model is that the internally rerouted customers do not arrive at the various queues according to a Poisson process, causing standard techniques to find waiting-time distributions to fail. In this paper we develop a new method to obtain exact expressions for the Laplace-Stieltjes transforms of the steady-state waiting-time distributions. This method can be applied to a wide variety of models which lacked an analysis of the waiting-time distribution until now

    Mixed Polling with Rerouting and Applications

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    Queueing systems with a single server in which customers wait to be served at a finite number of distinct locations (buffers/queues) are called discrete polling systems. Polling systems in which arrivals of users occur anywhere in a continuum are called continuous polling systems. Often one encounters a combination of the two systems: the users can either arrive in a continuum or wait in a finite set (i.e. wait at a finite number of queues). We call these systems mixed polling systems. Also, in some applications, customers are rerouted to a new location (for another service) after their service is completed. In this work, we study mixed polling systems with rerouting. We obtain their steady state performance by discretization using the known pseudo conservation laws of discrete polling systems. Their stationary expected workload is obtained as a limit of the stationary expected workload of a discrete system. The main tools for our analysis are: a) the fixed point analysis of infinite dimensional operators and; b) the convergence of Riemann sums to an integral. We analyze two applications using our results on mixed polling systems and discuss the optimal system design. We consider a local area network, in which a moving ferry facilitates communication (data transfer) using a wireless link. We also consider a distributed waste collection system and derive the optimal collection point. In both examples, the service requests can arrive anywhere in a subset of the two dimensional plane. Namely, some users arrive in a continuous set while others wait for their service in a finite set. The only polling systems that can model these applications are mixed systems with rerouting as introduced in this manuscript.Comment: to appear in Performance Evaluatio

    Waiting times in discrete-time cyclic-service systems

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    Single-served, multiqueue systems with cyclic service in discrete time are considered. Nonzero switchover times between consecutive queues are assumed; the service strategies at the various queues may differ. A decomposition for the amount of work in such systems is obtained, leading to an exact expression for a weighted sum of the mean waiting times at the various queues

    End-to-end delays in polling tree networks

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    We consider a tree network of polling stations operating in discrete-time. Packets arrive from external sources to the network according to batch Bernoulli arrival processes. We assume that all nodes have a service discipline that is HoL-based. The class of HoL-based service disciplines contains for instance the Bernoulli and limited service disciplines, and hence also the classical exhaustive and 1-limited. We obtain an exact expression for the overall mean end-to-end delay, and an approximation for the mean end-to-end delay of packets per source. The study is motivated by Networks on Chips where multiple processors share a single memory
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