Design of a low power switched-capacitor pipeline analog-to-digital converter

An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious. In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s. Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply. Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply

Hybrid receiver study

The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions

Migration of High Precision PulSAR Analog-to-Digital Converters to Blackfin-based Platforms

This Major Qualifying Project sought to migrate Analog Devices\u27 PulSAR line of ADCs to a more modern testing and evaluation platform, the SDP. The project resulted in more extensible daughter cards, a modular driver amplifier system, an integrated power supply design, and a software package to read and analyze the ADC data. Reference schematics were also developed and tested to showcase high performance and low power with the PulSAR converters

Magnetometric techniques for the measurement of initial susceptibility and for non-contact sensing of displacement

PhD ThesisPart 1 of the thesis describes a new instrument that simultaneously measures the real magnetic susceptibility X' and the imaginary magnetic susceptibility X". The instrument measures the temperature dependences of X' and X" in rock samples between 16°C and 800°C; natural developments are working down to -200°C and measuring the anisotropy of susceptibility. The instrument's heart is a tuned circuit driven at its natural frequency by a 5MHz crystal oscillator. The tuned circuit's inductance is a sample coil that encloses-a furnace. The random noise level in the signal for X' is 7.4 x l0-13 m3 r. m. s., the noise level in the signal for X" is 2x 10 ^12 m3 r. m. s. Sample volumes are 0.1 cm3 or less. Equations describing the instrument are derived and verified, particular attention is paid to the sample coil. Circuit diagrams are included. Some results are presented and equations that broadly describe the observed temperature dependences of X' and X" are developed. Some methods for substantially improving the instrument's performance are outlined. Part 2 of the thesis describes a new method for non-contact sensing of displacement. A magnet is mounted on the object whose displacement is to be measured. The magnet's field is sensed and fed to a 6502 microprocessor programmed to display the distance between the magnet and the sensor; intervening barriers with a permeability very close to unity do not affect the readings. The accuracy is better than 2.0% of full scale deflection (FSD) over the useful range of 250 mm and better than 0.1% FSD over a range of 110 mm. The magnet's volume is 4.00 mm3 and the moment is 3.1 x 10-7 Vbm. Circuit diagrams are presented and a complete software listing is included, the design will work with any magnet and magnetometer. There are directions for greatly improving the instrument's performance.Natural Environment Research Council

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

A comparison of DDS and DRFM techniques in the generation of "smart noise" jamming waveforms

This thesis presents a comparison of the effectiveness of 'smart noise' jamming waveforms against advanced threat radars, which are generated using either Direct Digital Synthesis (DDS) or Digital RF Memory (DRFM) based support jamming. The challenge lies in the fact the modern radar employs advanced waveforms, ultralow sidelobe antennas, coherent sidelobe cancelers, and sidelobe blankers to inhibit signals entering through its sidelobes. This thesis compares the effectiveness of using DDS versus DRFM techniques to meet this challenge. In particular, the effect of mismatched frequency on the DDS jamming waveform is described, as is the effect of quantization and multi-signal storage in the DRFM. A quantitative comparison of these jamming techniques against the AN/TPS-70 surveillance radar is madehttp://archive.org/details/comparisonofddsd00watsCaptain, United States ArmyApproved for public release; distribution is unlimited

Oversampling digital-to-analog converters

Oversampling and noise-shaping methods for digital-to-analog (D/A) conversion have been widely accepted as methods of choice in high performance data conversion applications. In this thesis, the fundamentals of D/A conversion and oversampling D/A conversion were discussed, along with the detailed analysis and comparison of the reported state-of-the-art oversampling D/A converters. Conventional oversampling D/A converters use 1-bit internal D/A conversion. Complex analog filters and/or large oversampling ratios are usually needed in these 1-bit oversampling D/A converters. Using multi-bit internal D/A conversion, the analog filter can be much simpler and the oversampling ratio can be greatly reduced. However, the linearity of the multi-bit D/A converter has to be at least the same as that required by the overall system. The dual-quantization technique developed in the course of this research provides a good alternative for implementing multi-bit oversampling D/A converters. The system uses two internal D/A converters; one is single-bit and the other is multi-bit. The single-bit D/A converter is used in a path called the signal path while the multi-bit D/A converter is used in a path called the correction path. Since the multi-bit D/A converter is not directly placed in the signal path, its nonlinearity error can be noise shaped by an analog differentiator so that the in-band noise contribution from the nonlinearity error is very small at the system output, greatly reducing the linearity requirement on the multi-bit internal D/A converter. An experimental implementation of an oversampling D/A converter using the dual-quantization technique was carried out to verify the concept. Despite about 10 dB higher noise than expected and the high second-order harmonic distortion due to practical problems in the implementation, the implemented system showed that the corrected output had more than 20 dB improvement over the uncorrected output in both signal-to-noise ratio and dynamic range, demonstrating the validity of the concept

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.

Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15