Coding scheme for 3D vertical flash memory

Recently introduced 3D vertical flash memory is expected to be a disruptive technology since it overcomes scaling challenges of conventional 2D planar flash memory by stacking up cells in the vertical direction. However, 3D vertical flash memory suffers from a new problem known as fast detrapping, which is a rapid charge loss problem. In this paper, we propose a scheme to compensate the effect of fast detrapping by intentional inter-cell interference (ICI). In order to properly control the intentional ICI, our scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. This technique is closely connected to the well-known problem of coding in a memory with defective cells. Numerical results show that the proposed scheme can effectively address the problem of fast detrapping.Comment: 7 pages, 9 figures. accepted to ICC 2015. arXiv admin note: text overlap with arXiv:1410.177

Nanoparticles as a charge trapping layer in Metal-Insulator-Semiconductor structures

Memories with floating gate structures are the main device architecture used in current non-volatile memories. Different films for floating gate based devices have been studied to substitute poly-crystalline silicon as the main material in floating gate structures. In current technology tunneling oxides are required to have thicknesses around 30 nm reducing device performance. Nanocrystals and nanoparticles have been emerging as a possible replacement for those films since better retention times and faster devices can be obtained. In this work the study of nanoparticles as the Charge trapping layer was executed. Study of the nanoparticles was made in a MIS structure. Hysteresis loops on C-V curves showing charge trapping was expected. Molybdenum film in the charge trapping layer was characterized as a comparison term for the nanoparticles in the CT-layer. Results of this work detail the importance of the interfacial layers, as well as defects across the oxides, on the electrical characterization of this structures. Hole trapping was achieved with nanoparticles as a charge trapping layer. Data obtained demonstrated the effect of interfacial defects in C-V curves as well as charging behavior in gold nanoparticles and Molybdenum films

Development of a Monolithically Integrated GaN Nanowire Memory Device

Gallium nitride (GaN) devices are of particular interest for a variety of fields and application spaces. The materials properties of GaN make it an ideal semiconductor for electronics and optoelectronics. Within electronics, GaN is of great interest for high-power and high-frequency electronics. Within optoelectronics, GaN has enabled efficient lighting and continues to be scaled for augmented reality and virtual reality (AR/VR) application spaces through the realization of micro-LEDs. In scaling such devices for incorporation into larger systems that span multiple fields, monolithically integrating other devices and components would provide greater flexibility and improve system-level performance. One such avenue for explored here is the development and integration of a GaN-based memory device with a light-emitting diode (LED). Specifically, a nanowire memory device integrated vertically with an LED. Initial work involved developing and verifying a high-κ dielectric memory stack on Si for memory characteristics. This was followed by fabrication of the integrated memory device and LED on a green LED GaN-on-sapphire substrate through a top-down approach. Initial electrical testing showed a functional, blue-shifted LED and the existence of a 2.5V memory window for a +/-10V program/erase window. Finally, a new self-limiting etch technique was examined to address possibilities for further scaling nanowires

Design and characterization of MIS devices

This work is a part of the research performed at the Research Laboratory of Electronics (Elektronfysik III), concerning [metal-insulator-semiconductor] MIS field-effect devices. It deals with the properties of different memory devices, such as the [metal-nitride-oxide-semiconductor] MNOS and the [floating-gate avalanche-injection metal-oxide-semiconductor] FAMOS memory transistors, where the [metal insulator semiconductor] MIS structure is utilized for information storage. Paper A describes a new associative memory cell in which MNOS transistors are used as storage elements. Paper B describes the Negative Bias Stress of MOS devices at high electric fields with respect to the degradation observed in MNOS memory devices repeatedly operated at high write/erase gate voltages. Paper C deals with the FAMOS memory device and how the information may be unintentionally changed after a large number of read cycles. Paper D is concerned with some critical problems during fabrication of low threshold voltage CMOS circuits for digital watch applications. Paper E shows the influence of a narrow channel width on the threshold voltage in MOS transistors when modulated by the substrate-source voltage

Commercialization of germanium based nanocrystal memory

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.This thesis explores the commercialization of germanium-based nanocrystal memories. Demand for smaller and faster electronics and embedded systems supports the development of high-density, low-power non-volatile electronic memory devices. Flash memory cells designed for ten years of data retention require the use of a thick tunneling oxide. This compromises writing and reading speed as well as endurance. A smaller device size can be achieved and speed and can be improved by decreasing the oxide thickness. However, significant charge leakage will occur if the oxide is too thin, which will reduce the data retention time dramatically. This imposes a limit to the amount by which the oxide thickness can be decreased in conventional devices. Research has shown that by incorporating nanocrystals in the tunnel oxide, charge traps are created which reduce charge leakage and improve endurance through charge-storage redundancy. By replacing the conventional floating gate memory with one using Si or Ge nanocrystals, the nonvolatile memory exhibits high programming speed with low programming voltage and superior retention time, and yet is compatible with conventional silicon technology. This thesis provides an analysis of competing technologies, an intellectual property analysis, costs modeling as well as ways to improve nanocrystal memories in order to compete with other forms of emerging technologies to replace conventional Flash memories.by Kian Chiew Seow.M.Eng

Fabrication of Al:HfO2 Gate Dielectric MOSFETs

Replacing the traditional SiO2 gate oxide in a MOSFET with ferroelectric HfO2 creates a 1T memory device referred to as a FeFET. The bi-stable polarization states cause a retained threshold voltage shift known as the memory window. Ferroelectric HfO2 offers a number of material and electrical advantages over perovskite based ferroelectrics such as PZT or SBT. Due to its use as a high-k dielectric, the ALD capability and etch characteristics of hafnium oxide are well documented. Ferroelectric HfO2 has been shown to be thermally stable up to 1000 C, making gate first FeFET processes feasible. Electrically, HfO2 is capable of achieving much larger memory windows due to a high coercive field, on the order of 1-2 MV/cm. This property also allows for much thinner films (\u3c30 \u3enm) without degradation of the memory window, and the potential for finFET applications. This work focuses on the integration of aluminum doped HfO2 into a standard RIT FET process. Previous work at RIT has led to the development of an ALD recipe and subsequent anneal to induce the ferroelectric crystal phase in Al:HfO2. In this work, n-channel MOSFETs with aluminum gate/20nm Al:HfO2/p-Si have been de- signed and fabricated. Etching of Al:HfO2 has been investigated using chlorine based plasma etching. The devices show a subthreshold slope of 75 mV/dec. Pulse testing reveals significant threshold voltage shift due to electron charge trapping commonly observed in Hf based dielectrics. I-V characteristics show mobility degradation, which is caused by Coulomb scattering as a result of trapped charges. For the devices to exhibit ferroelectric behavior with high on-state current, measurement and mitigation of charge trapping need to be further investigated

Flash-based security primitives: Evolution, challenges and future directions

Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration