13,039 research outputs found
On the AER Convolution Processors for FPGA
Image convolution operations in digital computer
systems are usually very expensive operations in terms of
resource consumption (processor resources and processing time)
for an efficient Real-Time application. In these scenarios the
visual information is divided into frames and each one has to be
completely processed before the next frame arrives in order to
warranty the real-time. A spike-based philosophy for computing
convolutions based on the neuro-inspired Address-Event-
Representation (AER) is achieving high performances. In this
paper we present two FPGA implementations of AER-based
convolution processors for relatively small Xilinx FPGAs
(Spartan-II 200 and Spartan-3 400), which process 64x64 images
with 11x11 convolution kernels. The maximum equivalent
operation rate that can be reached is 163.51 MOPS for 11x11
kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock.
Formulations, hardware architecture, operation examples and
performance comparison with frame-based convolution
processors are presented and discussed.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
Image convolution operations in digital computer systems are usually
very expensive operations in terms of resource consumption (processor
resources and processing time) for an efficient Real-Time application. In these
scenarios the visual information is divided in frames and each one has to be
completely processed before the next frame arrives. Recently a new method for
computing convolutions based on the neuro-inspired philosophy of spiking
systems (Address-Event-Representation systems, AER) is achieving high
performances. In this paper we present two FPGA implementations of AERbased
convolution processors that are able to work with 64x64 images and
programmable kernels of up to 11x11 elements. The main difference is the use
of RAM for integrators in one solution and the absence of integrators in the
second solution that is based on mapping operations. The maximum equivalent
operation rate is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400
FPGA with a 50MHz clock. Formulations, hardware architecture, operation
examples and performance comparison with frame-based convolution
processors are presented and discussed.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Junta de Andalucía P06-TIC-0141
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