466 research outputs found

    Manipulating Multistage Interconnection Networks Using Fundamental Arrangements

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    A hybrid queueing model for fast broadband networking simulation

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    PhDThis research focuses on the investigation of a fast simulation method for broadband telecommunication networks, such as ATM networks and IP networks. As a result of this research, a hybrid simulation model is proposed, which combines the analytical modelling and event-driven simulation modelling to speeding up the overall simulation. The division between foreground and background traffic and the way of dealing with these different types of traffic to achieve improvement in simulation time is the major contribution reported in this thesis. Background traffic is present to ensure that proper buffering behaviour is included during the course of the simulation experiments, but only the foreground traffic of interest is simulated, unlike traditional simulation techniques. Foreground and background traffic are dealt with in a different way. To avoid the need for extra events on the event list, and the processing overhead, associated with the background traffic, the novel technique investigated in this research is to remove the background traffic completely, adjusting the service time of the queues for the background traffic to compensate (in most cases, the service time for the foreground traffic will increase). By removing the background traffic from the event-driven simulator the number of cell processing events dealt with is reduced drastically. Validation of this approach shows that, overall, the method works well, but the simulation using this method does have some differences compared with experimental results on a testbed. The reason for this is mainly because of the assumptions behind the analytical model that make the modelling tractable. Hence, the analytical model needs to be adjusted. This is done by having a neural network trained to learn the relationship between the input traffic parameters and the output difference between the proposed model and the testbed. Following this training, simulations can be run using the output of the neural network to adjust the analytical model for those particular traffic conditions. The approach is applied to cell scale and burst scale queueing to simulate an ATM switch, and it is also used to simulate an IP router. In all the applications, the method ensures a fast simulation as well as an accurate result

    Management: A bibliography for NASA managers

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    This bibliography lists 731 reports, articles and other documents introduced into the NASA Scientific and Technical Information System in 1990. Items are selected and grouped according to their usefulness to the manager as manager. Citations are grouped into ten subject categories: human factors and personnel issues; management theory and techniques; industrial management and manufacturing; robotics and expert systems; computers and information management; research and development; economics, costs and markets; logistics and operations management; reliability and quality control; and legality, legislation, and policy

    RF-IV waveform engineering inspired MMIC design

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    The research work presented in this thesis sets out to investigate improvements to the power amplifier (PA) design cycle through the use of Waveform Engineering techniques. This is approached using alternative simulation methods with strong links to the data available from time domain based radio frequency waveform measurement and characterisation systems. One key objective of this work is to improve the overall efficiency of the radiofrequency power amplifier stage by focusing on circuit design. More specifically, the direct utilisation of waveform-engineering techniques in the development of multi-stage amplifiers to improve power added efficiency was targeted. In developing these power amplifier design methodologies, the techniques are demonstrated and validated using monolithic microwave integrated circuit (MMIC) implementation. This work has also led to an increase in understanding of the operation of the device terminal waveforms which is used to drive an alternative simulation approach. Through the use of standard computer-aided design (CAD) device models and measured waveform data, a 2-stage MMIC Gallium Nitride power amplifier has been detailed. This amplifier also uses internal node probe points in the interstage matching network, along with a new application of the waveform measurement system, to allow investigation of the terminal waveforms to validate the performance. This direct implementation of these waveform measurements provides valuable information on the design of the interstage networks to reduce the number of design iterations resulting in a more efficient design process. Waveform-engineering-based designs completed in this research have been demonstrated with test circuits and the time domain measurement system to demonstrate new modes of operation, as well as complete designs realised as prototype MMIC power amplifiers

    Switching techniques for broadband ISDN

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    The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

    Advances in Optical Amplifiers

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    Optical amplifiers play a central role in all categories of fibre communications systems and networks. By compensating for the losses exerted by the transmission medium and the components through which the signals pass, they reduce the need for expensive and slow optical-electrical-optical conversion. The photonic gain media, which are normally based on glass- or semiconductor-based waveguides, can amplify many high speed wavelength division multiplexed channels simultaneously. Recent research has also concentrated on wavelength conversion, switching, demultiplexing in the time domain and other enhanced functions. Advances in Optical Amplifiers presents up to date results on amplifier performance, along with explanations of their relevance, from leading researchers in the field. Its chapters cover amplifiers based on rare earth doped fibres and waveguides, stimulated Raman scattering, nonlinear parametric processes and semiconductor media. Wavelength conversion and other enhanced signal processing functions are also considered in depth. This book is targeted at research, development and design engineers from teams in manufacturing industry, academia and telecommunications service operators

    Report of the IEEE Workshop on Measurement and Modeling of Computer Dependability

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    Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNASA Langley Research Center / NASA NAG-1-602 and NASA NAG-1-613ONR / N00014-85-K-000
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