Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Caractérisation et modélisation d'interconnexions. Développement de nouvelles solutions pour la transmission d'informations au sein des cartes et puces électroniques.

Since the first IC in 1959 the performances and computing capacity of electronic devices have always grown, following thus the well-known empirical Moore’s law which says that the number of transistors in a dense integrated circuit doubles approximately every 18 months. This prevision is still verified even if some limitations appears like for example the limitation of the clock frequency which grow less than the projection that the ITRS (International Technology Roadmap for Semiconductors) has made in 2000. One of the stumbling point comes from interconnects which ensure the transmission of information inside electronic chips or cards. The interconnects imply delay, signal distortion, crosstalk and power dissipation and they now must be taken into account during electronic device design. So the researches depicted in this manuscript deal with the modelling of interconnect and study of new solutions to overcome problems due to classical interconnects. These works have been realized in Lab-STICC laboratory with the help of colleagues, post-doc, PhDs and Master Students. The manuscript include three chapters, the first one concerns researches on modelling aspects, the second is about alternative solutions to classical wired interconnects and to conclude the research projects for the next years are presented.The first chapter concern researches about modelling which aim to develop reliable models in view to simulate more quickly the electrical behavior of interconnects. Firstly the collaborations concerning the development of model-order reduction are presented. Then with the aim to evaluate the impact of inductive behavior, the current return patch problem and so the extraction of loop inductance is treated. The 3D discontinuities and 3D environment effects are presented in the third part of this chapter. For example the parallel grid influences on propagation are explored as well as the case of coupling between microvias and parallel-plates cavities inside multilayer PCB.The second chapter is about research of new solutions to overcome the limitation due to classical wired interconnects. A review of envisaged alternative solutions like for example optical interconnects and CNT (carbon Nano Tube) is first presented. Then a focus on RF guided interconnect is made and constraints in term of bandwidth are explained and some coupling techniques are explored. These studies naturally lead to exploration of the paradigm of wireless interconnects and the preliminary researches on radio transmission between two circuits placed on a PCB are shown. All these approaches of RF wireless interconnect are prelude to the research projects which are developed in a third chapter of the manuscript.The development of the draft over 4 years is based on the BBC project (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) funded by the Labex COMINLABS and which will begin in October 2016. The aims of this project are outlined as well as the aims of another project entitled “BROADWAYS” (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) which is currently in the second step of review by the ANR. To conclude this research part other embryonic researches are presented as well as long term researches envisaged like terahertz applications of the use of graphene for microwave applications.Depuis les premiers circuits intégrés en 1959 les composants et les systèmes électroniques n’ont cessé de voir leurs performances augmenter suivant ainsi la loi empirique de Gordon Moore qui prévoit un doublement de la complexité des circuits tous les 18 mois. Cette prévision reste aujourd’hui toujours vérifiée même si nous constatons depuis une dizaine d’années que les fréquences d’horloges stagnent autour de 4-5 GHz alors que l’ITRS (International Technology Roadmap for Semiconductors) prévoyait dans les années 2000 des fréquences de travail pouvant atteindre 40 GHz pour 2016. L’un des facteurs limitant la progression des performances vient des interconnexions métalliques servant au transport de l’information au sein des systèmes électroniques. Les travaux de recherche présentés dans le cadre de l’obtention de l‘habilitation à diriger des recherches concernent d’une part les travaux réalisés sur la modélisation des interconnexions et d’autre part ceux sur l’étude de solutions alternatives à ces interconnexions classiques. Ces travaux ont été réalisés au sein du Lab-STICC en collaboration avec plusieurs collègues et lors de l’encadrement de plusieurs post-doctorants, doctorants et stagiaires de master recherche. Le mémoire comporte trois chapitres principaux, le premier concerne les travaux sur la modélisation des interconnexions, le second porte sur l’étude de solutions alternatives à ces interconnexions classiques et le dernier permet la présentation des projets de recherches pour les prochaines années.L’objectif de nos travaux sur la modélisation des interconnexions consiste au développement de modèles fiables permettant d’appréhender leurs effets sur les signaux. Dans un premier temps, les travaux portant sur l’obtention de modèles à complexité réduite sont présentés. Puis, afin d’évaluer l’impact des effets inductifs des interconnexions, nous présentons les travaux sur l’identification des chemins de retours du courant dans un réseau comprenant plusieurs lignes et qui sont nécessaires pour déterminer les inductances de boucles. La prise en compte de l’environnement 3D des interconnexions fait l’objet de la troisième partie de ce chapitre. Nous traitons ainsi de l’influence de différentes discontinuités et nous présentons des règles de design permettant la limitation des risques de conversion de mode de propagation. Dans le cadre de structures multicouches, nous abordons l’influence de grilles métalliques placées au voisinage d’une ligne sur la propagation des signaux. Enfin nous traitons des risques de couplage entre des vias et les modes de cavités au sein des structures PCB multicouches.La seconde thématique développée dans ce mémoire porte sur le développement de solutions alternatives aux interconnexions classiques. Après avoir listé certaines de ces solutions telle que les interconnexions optiques ou les nanotubes de carbone, nous présentons plus particulièrement les interconnexions RF qui véhiculent l’information numérique sur porteuse à haute fréquence. Dans un premier temps nous analysons les interconnexions RF guidées qui utilisent une ligne de transmission comme support pour transporter l’information. A partir de l’étude des modes d’accès multiples nous montrons que les canaux doivent être large bande et nous explorons diverses façons de transmettre l’énergie à la ligne de transmission. Enfin nous présentons quelques exemples de performances obtenues à l’aide de démonstrateurs numériques. Ces études des interconnexions RF guidées nous ont naturellement amené à considérer les possibilités de transmission par voie hertzienne des informations au sein des cartes et puces électroniques. Nous avons ainsi analysé à l’aide de démonstrateurs très simples les niveaux de transmission entre deux circuits placés sur une même carte PCB (Printed Circuit Board).Ces études initiales sur les interconnexions radios ou sans fils servent de point d’appui aux projets de recherche présentés à la fin de ce manuscrit. La philosophie du projet BBC (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) financé par le Labex COMINLABS à partir d’octobre est présenté de même que celle du projet ANR Broadways (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) en seconde phase d’étude auprès de l’ANR

Economically sustainable public security and emergency network exploiting a broadband communications satellite

The research contributes to work in Rapid Deployment of a National Public Security and Emergency Communications Network using Communication Satellite Broadband. Although studies in Public Security Communication networks have examined the use of communications satellite as an integral part of the Communication Infrastructure, there has not been an in-depth design analysis of an optimized regional broadband-based communication satellite in relation to the envisaged service coverage area, with little or no terrestrial last-mile telecommunications infrastructure for delivery of satellite solutions, applications and services. As such, the research provides a case study of a Nigerian Public Safety Security Communications Pilot project deployed in regions of the African continent with inadequate terrestrial last mile infrastructure and thus requiring a robust regional Communications Satellite complemented with variants of terrestrial wireless technologies to bridge the digital hiatus as a short and medium term measure apart from other strategic needs. The research not only addresses the pivotal role of a secured integrated communications Public safety network for security agencies and emergency service organizations with its potential to foster efficient information symmetry amongst their operations including during emergency and crisis management in a timely manner but demonstrates a working model of how analogue spectrum meant for Push-to-Talk (PTT) services can be re-farmed and digitalized as a “dedicated” broadband-based public communications system. The network’s sustainability can be secured by using excess capacity for the strategic commercial telecommunication needs of the state and its citizens. Utilization of scarce spectrum has been deployed for Nigeria’s Cashless policy pilot project for financial and digital inclusion. This effectively drives the universal access goals, without exclusivity, in a continent, which still remains the least wired in the world

Proceedings of the Second International Mobile Satellite Conference (IMSC 1990)

Presented here are the proceedings of the Second International Mobile Satellite Conference (IMSC), held June 17-20, 1990 in Ottawa, Canada. Topics covered include future mobile satellite communications concepts, aeronautical applications, modulation and coding, propagation and experimental systems, mobile terminal equipment, network architecture and control, regulatory and policy considerations, vehicle antennas, and speech compression

Floorplan-Aware High Performance NoC Design

Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo para la inter-conexi-n de los diversos elementos de dichos sistemas. En este sentido, fabricantes de CMPs y MPSoCs han adoptado NoCs sencillas, generalmente con una topolog'a en malla o anillo, ya que son suficientes para satisfacer las necesidades de los sistemas actuales. Sin embargo a medida que los requerimientos del sistema -- baja latencia y alto rendimiento -- se hacen m�s exigentes, estas redes tan simples dejan de ser una soluci-n real. As', la comunidad investigadora ha propuesto y analizado NoCs m�s complejas. No obstante, estas soluciones son m�s dif'ciles de implementar -- especialmente los enlaces largos -- haciendo que este tipo de topolog'as complejas sean demasiado costosas o incluso inviables. En esta tesis, presentamos una metodolog'a de dise-o que minimiza la p�rdida de prestaciones de la red debido a su implementaci-n real. Los principales problemas que se encuentran al implementar una NoC son los conmutadores y los enlaces largos. En esta tesis, el conmutador se ha hecho modular, es decir, formado como uni-n de m-dulos m�s peque-os. En nuestro caso, los m-dulos son id�nticos, donde cada m-dulo es capaz de arbitrar, conmutar, y almacenar los mensajes que le llegan. Posteriormente, flexibilizamos la colocaci-n de estos m-dulos en el chip, permitiendo que m-dulos de un mismo conmutador est�n distribuidos por el chip. Esta metodolog'a de dise-o la hemos aplicado a diferentes escenarios. Primeramente, hemos introducido nuestro conmutador modular en NoCs con topolog'as conocidas como la malla 2D. Los resultados muestran como la modularidad y la distribuci-n del conmutador reducen la latencia y el consumo de potencia de la red. En segundo lugar, hemos utilizado nuestra metodolog'a de dise-o para implementar un crossbar distribuidRoca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17844Palanci

Spacelab system analysis: A study of communications systems for advanced launch systems

An analysis of the required performance of internal avionics data bases for future launch vehicles is presented. Suitable local area networks that can service these requirements are determined

Distributed Quantum Computation Architecture Using Semiconductor Nanophotonics

In a large-scale quantum computer, the cost of communications will dominate the performance and resource requirements, place many severe demands on the technology, and constrain the architecture. Unfortunately, fault-tolerant computers based entirely on photons with probabilistic gates, though equipped with "built-in" communication, have very large resource overheads; likewise, computers with reliable probabilistic gates between photons or quantum memories may lack sufficient communication resources in the presence of realistic optical losses. Here, we consider a compromise architecture, in which semiconductor spin qubits are coupled by bright laser pulses through nanophotonic waveguides and cavities using a combination of frequent probabilistic and sparse determinstic entanglement mechanisms. The large photonic resource requirements incurred by the use of probabilistic gates for quantum communication are mitigated in part by the potential high-speed operation of the semiconductor nanophotonic hardware. The system employs topological cluster-state quantum error correction for achieving fault-tolerance. Our results suggest that such an architecture/technology combination has the potential to scale to a system capable of attacking classically intractable computational problems.Comment: 29 pages, 7 figures; v2: heavily revised figures improve architecture presentation, additional detail on physical parameters, a few new reference

Spacelab system analysis: A study of the Marshall Avionics System Testbed (MAST)

An analysis of the Marshall Avionics Systems Testbed (MAST) communications requirements is presented. The average offered load for typical nodes is estimated. Suitable local area networks are determined