6,521 research outputs found
Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits
FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar
transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance
and resistance extraction is crucial in the design and verification of Fin-
FET integrated circuits. Though there are wide varieties of techniques available for
parasitic extraction, FinFETs still pose tremendous challenges due to the complex
geometries and user model of FinFETs. In this thesis, we propose three practical
techniques for parasitic extraction of FinFET integrated circuits.
The first technique we propose is to solve the dilemma that foundries and IP
vendors face to protect the sensitive information which is prerequisite for accurate
parasitic extraction. We propose an innovative solution to the challenge, by building
a macro model around any region in 2D/3D on a circuit where foundries or IP
vendors wish to hide information, yet the macro model allows accurate capacitance
extraction inside and outside of the region.
The second technique we present is to reduce the truncation error introduced by
the traditional Neumann boundary condition. We make a fundamental contribution
to the theory of field solvers by proposing a class of absorbing boundary conditions,
which when placed on the boundary of the numerical region, will act as if the region
extends to infinity. As a result, we can significantly reduce the size of the numerical
region, which in turn reduces the run time without sacrificing accuracy.
Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance
of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM.
The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example
Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits
FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar
transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance
and resistance extraction is crucial in the design and verification of Fin-
FET integrated circuits. Though there are wide varieties of techniques available for
parasitic extraction, FinFETs still pose tremendous challenges due to the complex
geometries and user model of FinFETs. In this thesis, we propose three practical
techniques for parasitic extraction of FinFET integrated circuits.
The first technique we propose is to solve the dilemma that foundries and IP
vendors face to protect the sensitive information which is prerequisite for accurate
parasitic extraction. We propose an innovative solution to the challenge, by building
a macro model around any region in 2D/3D on a circuit where foundries or IP
vendors wish to hide information, yet the macro model allows accurate capacitance
extraction inside and outside of the region.
The second technique we present is to reduce the truncation error introduced by
the traditional Neumann boundary condition. We make a fundamental contribution
to the theory of field solvers by proposing a class of absorbing boundary conditions,
which when placed on the boundary of the numerical region, will act as if the region
extends to infinity. As a result, we can significantly reduce the size of the numerical
region, which in turn reduces the run time without sacrificing accuracy.
Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance
of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM.
The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example
Compact modelling in RF CMOS technology
With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work
Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks
One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result
Ultrathin compound semiconductor on insulator layers for high performance nanoscale transistors
Over the past several years, the inherent scaling limitations of electron
devices have fueled the exploration of high carrier mobility semiconductors as
a Si replacement to further enhance the device performance. In particular,
compound semiconductors heterogeneously integrated on Si substrates have been
actively studied, combining the high mobility of III-V semiconductors and the
well-established, low cost processing of Si technology. This integration,
however, presents significant challenges. Conventionally, heteroepitaxial
growth of complex multilayers on Si has been explored. Besides complexity, high
defect densities and junction leakage currents present limitations in the
approach. Motivated by this challenge, here we utilize an epitaxial transfer
method for the integration of ultrathin layers of single-crystalline InAs on
Si/SiO2 substrates. As a parallel to silicon-on-insulator (SOI) technology14,we
use the abbreviation "XOI" to represent our compound semiconductor-on-insulator
platform. Through experiments and simulation, the electrical properties of InAs
XOI transistors are explored, elucidating the critical role of quantum
confinement in the transport properties of ultrathin XOI layers. Importantly, a
high quality InAs/dielectric interface is obtained by the use of a novel
thermally grown interfacial InAsOx layer (~1 nm thick). The fabricated FETs
exhibit an impressive peak transconductance of ~1.6 mS/{\mu}m at VDS=0.5V with
ON/OFF current ratio of greater than 10,000 and a subthreshold swing of 107-150
mV/decade for a channel length of ~0.5 {\mu}m
Reconfigurable nanoelectronics using graphene based spintronic logic gates
This paper presents a novel design concept for spintronic nanoelectronics
that emphasizes a seamless integration of spin-based memory and logic circuits.
The building blocks are magneto-logic gates based on a hybrid
graphene/ferromagnet material system. We use network search engines as a
technology demonstration vehicle and present a spin-based circuit design with
smaller area, faster speed, and lower energy consumption than the
state-of-the-art CMOS counterparts. This design can also be applied in
applications such as data compression, coding and image recognition. In the
proposed scheme, over 100 spin-based logic operations are carried out before
any need for a spin-charge conversion. Consequently, supporting CMOS
electronics requires little power consumption. The spintronic-CMOS integrated
system can be implemented on a single 3-D chip. These nonvolatile logic
circuits hold potential for a paradigm shift in computing applications.Comment: 14 pages (single column), 6 figure
A scalable model of the substrate network in deep N-Well RF MOSFETs with multiple fingers
A novel scalable model of substrate components for deep n-well (DNW) RF MOSFETs with different number
of fingers is presented for the first time. The test structure developed in [1] is employed to directly access
the characteristics of the substrate to extract the different substrate components. A methodology is developed
to directly extract the parameters for the substrate network from the measured data. By using the measured
two-port data of a set of nMOSFETs with different number of fingers, with the DNW in grounded and float
configuration, respectively, the parameters of the scalable substrate model are obtained. The method and the
substrate model are further verified and validated by matching the measured and simulated output admittances.
Excellent agreement up to 40 GHz for configurations in common-source has been achieved
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