217 research outputs found

    Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors

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    Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above

    Maxed Out: Massachusetts Transportation at a Financing Crossroad

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    Outlines the economic, environmental, and quality-of-life implications of the state's transportation revenue shortfalls; background and contributing factors; outcomes of reform efforts; and suggested guidelines for public policy discussions

    An integrated model for asset reliability, risk and production efficiency management in subsea oil and gas operations

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    PhD ThesisThe global demand for energy has been predicted to rise by 56% between 2010 and 2040 due to industrialization and population growth. This continuous rise in energy demand has consequently prompted oil and gas firms to shift activities from onshore oil fields to tougher terrains such as shallow, deep, ultra-deep and arctic fields. Operations in these domains often require deployment of unconventional subsea assets and technology. Subsea assets when installed offshore are super-bombarded by marine elements and human factors which increase the risk of failure. Whilst many risk standards, asset integrity and reliability analysis models have been suggested by many previous researchers, there is a gap on the capability of predictive reliability models to simultaneously address the impact of corrosion inducing elements such as temperature, pressure, pH corrosion on material wear-out and failure. There is also a gap in the methodology for evaluation of capital expenditure, human factor risk elements and use of historical data to evaluate risk. This thesis aims to contribute original knowledge to help improve production assurance by developing an integrated model which addresses pump-pipe capital expenditure, asset risk and reliability in subsea systems. The key contributions of this research is the development of a practical model which links four sub-models on reliability analysis, asset capital cost, event risk severity analysis and subsea risk management implementation. Firstly, an accelerated reliability analysis model was developed by incorporating a corrosion covariate stress on Weibull model of OREDA data. This was applied on a subsea compression system to predict failure times. A second methodology was developed by enhancing Hubbert oil production forecast model, and using nodal analysis for asset capital cost analysis of a pump-pipe system and optimal selection of best option based on physical parameters such as pipeline diameter, power needs, pressure drop and velocity of fluid. Thirdly, a risk evaluation method based on the mathematical determinant of historical event magnitude, frequency and influencing factors was developed for estimating the severity of risk in a system. Finally, a survey is conducted on subsea engineers and the results along with the previous models were developed into an integrated assurance model for ensuring asset reliability and risk management in subsea operations. A guide is provided for subsea asset management with due consideration to both technical and operational perspectives. The operational requirements of a subsea system can be measured, analysed and improved using the mix of mathematical, computational, stochastic and logical frameworks recommended in this work

    Mechanistic modeling of architectural vulnerability factor

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    Reliability to soft errors is a significant design challenge in modern microprocessors owing to an exponential increase in the number of transistors on chip and the reduction in operating voltages with each process generation. Architectural Vulnerability Factor (AVF) modeling using microarchitectural simulators enables architects to make informed performance, power, and reliability tradeoffs. However, such simulators are time-consuming and do not reveal the microarchitectural mechanisms that influence AVF. In this article, we present an accurate first-order mechanistic analytical model to compute AVF, developed using the first principles of an out-of-order superscalar execution. This model provides insight into the fundamental interactions between the workload and microarchitecture that together influence AVF. We use the model to perform design space exploration, parametric sweeps, and workload characterization for AVF

    Down Time Terms and Information Used for Assessment of Equipment Reliability and Maintenance Performance

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    Reliability and maintenance data is important for predictive analysis related to equipment downtime in the oil and gas industry. For example, downtime data together with equipment reliability data is vital for improving system designs, for optimizing maintenance and in estimating the potential for hazardous events that could harm both people and the environment. The quality is largely influenced by the repair time taxonomy, such as the measures used to define downtime linked to equipment failures. However, although it is important to achieve high quality from maintenance operations as part of this picture, these often seem to receive less focus compared to reliability aspects. Literature and experiences from, e.g., the OREDA project suggest several challenging issues, which we discuss in this chapter, e.g., for the interpretation of “MTTR.” Another challenge relates to the duration of maintenance activities. For example, while performing corrective maintenance on an item, one could also be working on several other items while being on site. This provides an opening for different ways of recording the mobilization time and repair time, which may then influence the data used for predictive analysis. Some relevant examples are included to illustrate some of the challenges posed, and some remedial actions are proposed

    Market-Based Resourse Management for Many-Core Systems

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    101 σ.Αντικείμενο της διπλωματικής αποτελεί η μελέτη και η ανάπτυξη μιας κλιμακώσιμης και κατανεμημένης πλατφόρμας (framework) διαχείρισης πόρων σε χρόνο εκτέλεσης για συστήματα πολλαπλών πυρήνων. Σε αυτήν την πλατφόρμα η διαχείριση πόρων είναι βασισμένη σε μοντέλα, τα οποία είναι εμπνευσμένα από την οικονομία. Παρουσιάζεται ένας διαχειριστής πόρων, ο οποίος προσφέρει ένα περιβάλλον διαχείρισης πόρων και εφαρμογών καθ ́ όλη τη διάρκεια ζωής τους, στο οποίο η κατανομή και δρομολόγηση των εφαρμογών στους πόρους πραγματοποιείται με αλγόριθμους βασισμένους σε κανόνες αγοράς. Η αποδοτικότητα κάθε μοντέλου αξιολογείται βάσει της πτώσης της αξιοπιστίας των πόρων (μετρική MTTF-Mean Time To Failure).The purpose of this diploma thesis is the design and development of a scalable and distributed run-time resource management framework for Many-core systems. In this framework, resource management is based on economy-inspired models. The presented resource management framework offers an environment that manages both application tasks and resources at run-time, matches and distributes application tasks across resources with algorithms which are based on market principles. The efficiency of each model is evaluated with respect to resource reliability degradation (metric MTTF-Mean Time to Failure).Θεμιστοκλής Γ. Μελισσάρη

    Improving the Reliability of Microprocessors under BTI and TDDB Degradations

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    Reliability is a fundamental challenge for current and future microprocessors with advanced nanoscale technologies. With smaller gates, thinner dielectric and higher temperature microprocessors are vulnerable under aging mechanisms such as Bias Temperature Instability (BTI) and Temperature Dependent Dielectric Breakdown (TDDB). Under continuous stress both parametric and functional errors occur, resulting compromised microprocessor lifetime. In this thesis, based on the thorough study on BTI and TDDB mechanisms, solutions are proposed to mitigating the aging processes on memory based and random logic structures in modern out-of-order microprocessors. A large area of processor core is occupied by memory based structure that is vulnerable to BTI induced errors. The problem is exacerbated when PBTI degradation in NMOS is as severe as NBTI in PMOS in high-k metal gate technology. Hence a novel design is proposed to recover 4 internal gates within a SRAM cell simultaneously to mitigate both NBTI and PBTI effects. This technique is applied to both the L2 cache banks and the busy function units with storage cells in out-of-order pipeline in two different ways. For the L2 cache banks, redundant cache bank is added exclusively for proactive recovery rotation. For the critical and busy function units in out-of-order pipelines, idle cycles are exploited at per-buffer-entry level. Different from memory based structures, combinational logic structures such as function units in execution stage can not use low overhead redundancy to tolerate errors due to their irregular structure. A design framework that aims to improve the reliability of the vulnerable functional units of a processor core is designed and implemented. The approach is designing a generic function unit (GFU) that can be reconfigured to replace a particular functional unit (FU) while it is being recovered for improved lifetime. Although flexible, the GFU is slower than the original target FUs. So GFU is carefully designed so as to minimize the performance loss when it is in-use. More schemes are also designed to avoid using the GFU on performance critical paths of a program execution

    Fault- and Yield-Aware On-Chip Memory Design and Management

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    Ever decreasing device size causes more frequent hard faults, which becomes a serious burden to processor design and yield management. This problem is particularly pronounced in the on-chip memory which consumes up to 70% of a processor' s total chip area. Traditional circuit-level techniques, such as redundancy and error correction code, become less effective in error-prevalent environments because of their large area overhead. In this work, we suggest an architectural solution to building reliable on-chip memory in the future processor environment. Our approaches have two parts, a design framework and architectural techniques for on-chip memory structures. Our design framework provides important architectural evaluation metrics such as yield, area, and performance based on low level defects and process variations parameters. Processor architects can quickly evaluate their designs' characteristics in terms of yield, area, and performance. With the framework, we develop architectural yield enhancement solutions for on-chip memory structures including L1 cache, L2 cache and directory memory. Our proposed solutions greatly improve yield with negligible area and performance overhead. Furthermore, we develop a decoupled yield model of compute cores and L2 caches in CMPs, which show that there will be many more L2 caches than compute cores in a chip. We propose efficient utilization techniques for excess caches. Evaluation results show that excess caches significantly improve overall performance of CMPs
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