23 research outputs found
Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
Design methodology for reliable and energy efficient self-tuned on-chip voltage regulators
The energy-efficiency needs in computing systems, ranging from high performance processors to low-power devices is steadily on the rise, resulting in increasing popularity of on-chip voltage regulators (VR). The high-frequency and high bandwidth on-chip voltage regulators such as Inductive voltage regulators (IVR) and Digital Low Dropout regulators (DLDO) significantly enhance the energy-efficiency of a SoC by reducing supply noise and enabling faster voltage transitions. However, IVRs and DLDOs need to cope with the higher variability that exists in the deep nanometer digital nodes since they are fabricated on the same die as the digital core affecting performance of both the VR and digital core. Moreover, in most modern SoCs where multiple power domains are preferred, each VR needs to be designed and optimized for a target load demand which significantly increases the design time and time to market for VR assisted SoCs. This thesis investigates a performance-based auto-tuning algorithm utilizing performance of digital core to tune VRs against variations and improve performance of both VR and the core. We further propose a fully synthesizable VR architecture and an auto-generation tool flow that can be used to design and optimize a VR for given target specifications and auto-generate a GDS layout. This would reduce the design time drastically. And finally, a flexible precision IVR architecture is also explored to further improve transient performance and tolerance to process variations. The proposed IVR and DLDO designs with an AES core and auto-tuning circuits are prototyped in two testchips in 130nm CMOS process and one test chip in 65nm CMOS process. The measurements demonstrate improved performance of IVR and AES core due to performance-based auto-tuning. Moreover, the synthesizable architectures of IVR and DLDO implemented using auto-generation tool flow showed competitive performance with state of art full custom designs with orders of magnitude reduction in design time. Additional improvement in transient performance of IVR is also observed due to the flexible precision feedback loop design.Ph.D
Modeling of magnetization dynamics and applications to spin-based logic and memory devices
The objective of this research is to develop models to better evaluate the performance and reliability of proposed spin-based boolean devices. This research will focus on a particular spin-based logic technology called Spin-Switch Logic. There are two primary reversal mechanisms that will be considered for a full evaluation of Spin-Switch technology. Firstly, nanomagnet reversal through the use of spin-transfer torque (STT) is studied. While switching through STT has been analytically solved for the uniaxial nanomagnet case, the biaxial case has yet to be studied on a sufficient scale and will be a focus of this research.
Secondly, input-output isolation is achieved through dipolar coupling; hence, the performance and reliability of this type of reversal mechanism is extensively studied. It is shown that dipolar coupling strength is not only a function of geometric and material parameters, but also of reversal speed. If the reversal of a neighboring nanomagnet is very fast, the dipolar field reduces to a constant longitudinal field and can be analytically studied. However, if the reversal of the neighboring nanomagnet is slow, new models are needed to estimate the region of reliable coupling and delay.
Lastly, a focal point of this research will be on the reliability of nanomagnet states in the presence of thermal noise and new models are proposed to estimate the reliability of complex spin-based systems. Not only does the thermal noise affect the probability of magnetization state consistency, it also alters nanomagnet precession during reversal, making the delay a random variable. Hence, models are developed for evaluating the variation in reversal delay through STT for both uniaxial and biaxial cases.
Ultimately, these analytic models are combined to comprehensively evaluate the performance of Spin-Switch technology and identify possible improvements to this technology. While the end result of this research will be a thorough analysis of Spin-Switch logic, the models developed during this research are applicable to a variety of spin-based logic and memory technologies.Ph.D
The impact of design techniques in the reduction of power consumption of SoCs Multimedia
Orientador: Guido Costa Souza de AraújoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projetoAbstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project scheduleMestradoCiência da ComputaçãoMestre em Ciência da Computaçã
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity
Various side-channel attacks (SCAs) on ICs have been successfully
demonstrated and also mitigated to some degree. In the context of 3D ICs,
however, prior art has mainly focused on efficient implementations of classical
SCA countermeasures. That is, SCAs tailored for up-and-coming 3D ICs have been
overlooked so far. In this paper, we conduct such a novel study and focus on
one of the most accessible and critical side channels: thermal leakage of
activity and power patterns. We address the thermal leakage in 3D ICs early on
during floorplanning, along with tailored extensions for power and thermal
management. Our key idea is to carefully exploit the specifics of material and
structural properties in 3D ICs, thereby decorrelating the thermal behaviour
from underlying power and activity patterns. Most importantly, we discuss
powerful SCAs and demonstrate how our open-source tool helps to mitigate them.Comment: Published in Proc. Design Automation Conference, 201
MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications
Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C
Floorplan and Power/Ground Network Co-Synthesis for Multipleupply Voltage Designs
隨著製程的縮小,電壓降在先進積體電路設計中已成為非常重要的議題。由於傳統的電壓降分析方式相當耗時,傳統分析方式並不適合應用在平面規劃與電源供應網的同步共同合成上。在另一方面,多重供應電壓設計使得電源供應網路上電壓降分析變得更加複雜。因此,在這篇論文中,我們首先提出一個十分有效率並且合理的電壓降模型。基於我們所提出的電壓降模型,針對使用多重電壓的電路設計,我們設計出一個非常有效且快速的平面規劃演算法。更明確地說,我們的演算法包含了一個以最小化平面周長為目標的平面擺放器,一個線性時間的電路區塊相鄰圖建造器以及一個電壓島群集器。在平面規劃完之後,基於使用線性規劃技巧的基礎上,我們提出一套可以同時擺放電源供應墊以及重新分布空白區域的演算法去進一步降低電壓降效應。實驗結果驗證了我們所提出的電壓降模型也顯示我們的演算法可以大量加速平面規劃的收斂速度並且有效降低電壓降效應。With technology scaling, the voltage (IR) drop in the power/ground (P/G) network becomes a crucial problem in modern IC designs. Since traditional IR-drop analysis methods are often very time-consuming, it is not feasible to apply traditional IR-drop analysis methods to co-synthesize the P/G network and floorplans. On the other hand, multiple-supply-voltage (MSV) designs further complicate the IR-drop analysis in the P/G network. Therefore, in this thesis, we first propose an efficient, yet reasonable IR-drop model. Based on the proposed IR-drop model, we present an efficient and effective floorplanning algorithm considering the IR-drop effect and the P/G network routing resource for designs with wire-bonding packaged power networks. Specifically, a perimeter-driven floorplanner, a linear-time block-adjacency-graph constructor, and a voltage-island clustering technique areresented. After floorplanning, we develop a linear programming based algorithm to perform simultaneous power-pad placement and whitespace redistribution for the IR-drop reduction. Experimental results validate the proposed IR-drop model and show that our algorithms can significantly improve the floorplanning convergence and effectively reduce the IR-drop cost for MSV designs.Table of Contentscknowledgements ibstract (Chinese) iibstract iiiist of Figures viiist of Tables xhapter 1. Introduction 1.1 Floorplan and Power/Ground Network Co-synthesis . . . . . . . . . . . . 1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Design Flows Considering the Power Integrity . . . . . . . . . . . . 3.2.2 Floorplan-Based P/G Network Planning Methodology for Singleupply Voltage Designs . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Floorplan and P/G Network Synthesis for Single Supply Voltageesigns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Voltage-Island Aware Floorplanning Methodology for Multiple Sup-ly Voltage Designs . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Power-Pad Placement Optimization . . . . . . . . . . . . . . . . . 5.2.6 Whitespace Redistribution for Wirelength Minimization . . . . . . 6.3 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8hapter 2. Preliminaries 9.1 Proposed IR-drop Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Floorplanning Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . 13hapter 3. Problem Formulation 14.1 Perimeter-Driven IR-Drop Constrained Floorplanning . . . . . . . . . . . 14.2 Post-Floorplanning Re?nement for IR-Drop Reduction . . . . . . . . . . 16hapter 4. Perimeter-Driven IR-Drop Constrained Floorplanning 19.1 Perimeter-Driven Formulation . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Block-Adjacency Graph Construction . . . . . . . . . . . . . . . . . . . . 23.3 Voltage-Island Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.4 Power-Pad Reachability Constraint Checking . . . . . . . . . . . . . . . . 31.5 Voltage Islands Merging by Whitespace Distribution . . . . . . . . . . . . 34hapter 5. Power-Pad Placement and Whitespace Redistribution 35.1 Monotone Power Network . . . . . . . . . . . . . . . . . . . . . . . . . . 35.2 Linear Programming Formulation . . . . . . . . . . . . . . . . . . . . . . 40hapter 6. Experimental Results 44.1 IR-Drop Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . 44.2 Perimeter-Driven Floorplanning . . . . . . . . . . . . . . . . . . . . . . . 46.3 Floorplanning with Voltage-Island Clustering . . . . . . . . . . . . . . . . 47.4 IR-Drop Constrained Floorplanning . . . . . . . . . . . . . . . . . . . . . 49.5 Post-Floorplanning Re?nement for IR-Drop Reduction . . . . . . . . . . 53hapter 7. Conclusions and Future Work 55ibliography 5