Compression of MRI brain images based on automatic extraction of tumor region

In the compression of medical images, region of interest (ROI) based techniques seem to be promising, as they can result in high compression ratios while maintaining the quality of region of diagnostic importance, the ROI, when image is reconstructed. In this article, we propose a set-up for compression of brain magnetic resonance imaging (MRI) images based on automatic extraction of tumor. Our approach is to first separate the tumor, the ROI in our case, from brain image, using support vector machine (SVM) classification and region extraction step. Then, tumor region (ROI) is compressed using Arithmetic coding, a lossless compression technique. The non-tumorous region, non-region of interest (NROI), is compressed using a lossy compression technique formed by a combination of discrete wavelet transform (DWT), set partitioning in hierarchical trees (SPIHT) and arithmetic coding (AC). The classification performance parameters, like, dice coefficient, sensitivity, positive predictive value and accuracy are tabulated. In the case of compression, we report, performance parameters like mean square error and peak signal to noise ratio for a given set of bits per pixel (bpp) values. We found that the compression scheme considered in our setup gives promising results as compared to other schemes

9/7 LIFT Reconfigurable Architecture Implementation for Image Authentication

Considering the information system medical images are the most sensitive and critical types of data. Transferring medical images over the internet requires the use of authentication algorithms that are resistant to attacks. Another aspect is confidentiality for secure storage and transfer of medical images. The proposed study presents an embedding technique to improve the security of medical images. As a part of preprocessing that involves removing the high-frequency components, Gaussian filters are used. To get LL band features CDF9/7 wavelet is employed. In a similar way, for the cover image, the LL band features are obtained. In order to get the 1st level of encryption the technique of alpha blending is used. It combines the LL band features of the secret image and cover images whereas LH, HL, and HH bands are applied to Inverse CDF 9/7. The resulting encrypted image along with the key obtained through LH, HL, and HH bands is transferred. The produced key adds an extra layer of protection, and similarly, the receiver does the reverse action to acquire the original secret image. The PSNR acquired from the suggested technique is compared to PSNR obtained from existing techniques to validate the results. Performance is quantified in terms of PSNR. A Spartan 6 FPGA board is used to synthesize the complete architecture in order to compare hardware consumption

Timing-Error Tolerance Techniques for Low-Power DSP: Filters and Transforms

Low-power Digital Signal Processing (DSP) circuits are critical to commercial System-on-Chip design for battery powered devices. Dynamic Voltage Scaling (DVS) of digital circuits can reclaim worst-case supply voltage margins for delay variation, reducing power consumption. However, removing static margins without compromising robustness is tremendously challenging, especially in an era of escalating reliability concerns due to continued process scaling. The Razor DVS scheme addresses these concerns, by ensuring robustness using explicit timing-error detection and correction circuits. Nonetheless, the design of low-complexity and low-power error correction is often challenging. In this thesis, the Razor framework is applied to fixed-precision DSP filters and transforms. The inherent error tolerance of many DSP algorithms is exploited to achieve very low-overhead error correction. Novel error correction schemes for DSP datapaths are proposed, with very low-overhead circuit realisations. Two new approximate error correction approaches are proposed. The first is based on an adapted sum-of-products form that prevents errors in intermediate results reaching the output, while the second approach forces errors to occur only in less significant bits of each result by shaping the critical path distribution. A third approach is described that achieves exact error correction using time borrowing techniques on critical paths. Unlike previously published approaches, all three proposed are suitable for high clock frequency implementations, as demonstrated with fully placed and routed FIR, FFT and DCT implementations in 90nm and 32nm CMOS. Design issues and theoretical modelling are presented for each approach, along with SPICE simulation results demonstrating power savings of 21 – 29%. Finally, the design of a baseband transmitter in 32nm CMOS for the Spectrally Efficient FDM (SEFDM) system is presented. SEFDM systems offer bandwidth savings compared to Orthogonal FDM (OFDM), at the cost of increased complexity and power consumption, which is quantified with the first VLSI architecture