Monolithic ultrasound fingerprint sensor.

This paper presents a 591×438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110×56-PMUT array, composed of 30×43-μm2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa-1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm×3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints

Design Considerations and Thermodynamic Feasibility Study of a Meso-scale Refrigerator

Recent advances in micro-fabrication technology have ushered a new era in miniaturization of chemical, environmental and energy systems. This foreseeable trend towards miniaturization in chemical, environmental and mechanical systems is expected to revolutionize the ways the human life is being perceived today. The high volume and mass reproducibility is seen as the striking aspect of micro-fabrication based miniature systems, offering economies far exceeding than the economies of scale obtained in large plants. The focus of this thesis work is directed at the thermodynamic feasibility and preliminary prototype design for a meso-scale refrigerator. Miniaturization to sub-centimeter domain will enable configuring these refrigerator units as sheet architectures integrated in layers, facilitating efficient local control of temperature. In the design abstraction, the entire refrigeration unit, comprising motor-compressor, evaporator, condenser, valves and fluidic control, is to be fabricated from several layers of bonded silicon wafers. The material treated in this thesis provides a perspective on the actuation mechanism of the integrated rotor-compressor through an axial-drive high-throughput variable capacitance electrostatic disk motor and underlying stator assembly. The design optimization of the motor actuation dynamics to extract optimal set of design parameters is provided to yield reasonably good output power of the compressor

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Modeling and analysis of thick suspended deep x-ray liga inductors on CMOS/BiCMOS substrate

Modeling and simulation results for two types of 150 &#956;m height air suspended inductors proposed for LIGA fabrication are presented. The inductor substrates used model the TSMC 0.18 &#956;m CMOS/BiCMOS substrates. The RF performance between the suspended structure and the unsuspended counterpart are compared and the advantage of the suspended structures is explored. The potential of LIGA for fabricating high suspended inductors with good performance and for combining these with CMOS/BiCMOS is demonstrated

FLEXIBLE LOW-COST HW/SW ARCHITECTURES FOR TEST, CALIBRATION AND CONDITIONING OF MEMS SENSOR SYSTEMS

During the last years smart sensors based on Micro-Electro-Mechanical systems (MEMS) are widely spreading over various fields as automotive, biomedical, optical and consumer, and nowadays they represent the outstanding state of the art. The reasons of their diffusion is related to the capability to measure physical and chemical information using miniaturized components. The developing of this kind of architectures, due to the heterogeneities of their components, requires a very complex design flow, due to the utilization of both mechanical parts typical of the MEMS sensor and electronic components for the interfacing and the conditioning. In these kind of systems testing activities gain a considerable importance, and they concern various phases of the life-cycle of a MEMS based system. Indeed, since the design phase of the sensor, the validation of the design by the extraction of characteristic parameters is important, because they are necessary to design the sensor interface circuit. Moreover, this kind of architecture requires techniques for the calibration and the evaluation of the whole system in addition to the traditional methods for the testing of the control circuitry. The first part of this research work addresses the testing optimization by the developing of different hardware/software architecture for the different testing stages of the developing flow of a MEMS based system. A flexible and low-cost platform for the characterization and the prototyping of MEMS sensors has been developed in order to provide an environment that allows also to support the design of the sensor interface. To reduce the reengineering time requested during the verification testing a universal client-server architecture has been designed to provide a unique framework to test different kind of devices, using different development environment and programming languages. Because the use of ATE during the engineering phase of the calibration algorithm is expensive in terms of ATE’s occupation time, since it requires the interruption of the production process, a flexible and easily adaptable low-cost hardware/software architecture for the calibration and the evaluation of the performance has been developed in order to allow the developing of the calibration algorithm in a user-friendly environment that permits also to realize a small and medium volume production. The second part of the research work deals with a topic that is becoming ever more important in the field of applications for MEMS sensors, and concerns the capability to combine information extracted from different typologies of sensors (typically accelerometers, gyroscopes and magnetometers) to obtain more complex information. In this context two different algorithm for the sensor fusion has been analyzed and developed: the first one is a fully software algorithm that has been used as a means to estimate how much the errors in MEMS sensor data affect the estimation of the parameter computed using a sensor fusion algorithm; the second one, instead, is a sensor fusion algorithm based on a simplified Kalman filter. Starting from this algorithm, a bit-true model in Mathworks Simulink(TM) has been created as a system study for the implementation of the algorithm on chip

Towards an on-chip power supply: Integration of micro energy harvesting and storage techniques for wireless sensor networks

The lifetime of a power supply in a sensor node of a wireless sensor network is the decisive factor in the longevity of the system. Traditional Li-ion batteries cannot fulfill the demands of sensor networks that require a long operational duration. Thus, we require a solution that produces its own electricity from its surrounding and stores it for future utility. Moreover, as the sensor node architecture is developed on complimentary metal-oxide-semiconductor technology (CMOS), the manufacture of the power supply must be compatible with it. In this thesis, we shall describe the components of an on-chip lifetime power supply that can harvest the vibrational mechanical energy through piezoelectric microcantilevers and store it in a reduced graphene oxide (rGO) based microsupercapacitor, and that is fabricated through CMOS compatible techniques. Our piezoelectric microcantilevers confirm the feasibility of fabricating micro electro- mechanical-systems (MEMS) size two-degree-of-freedom systems which can solve the major issue of small bandwidth of piezoelectric micro-energy harvesters. These devices use a cut-out trapezoidal cantilever beam to enhance the stress on the cantilever’s free end while reducing the gap remarkably between its first two eigenfrequencies in 400 - 500 Hz and 1 - 2 kHz range. The energy from the M-shaped harvesters will be stored in rGO based microsupercapacitors. These microsupercapacitors are manufactured through a fully CMOS compatible, reproducible, and reliable micromachining processes. Furthermore, we have also demonstrated an improvement in their electrochemical performance and yield of fabrication through surface roughening from iron nanoparticles. We have also examined the possibility of integrating these devices into a power management unit to fully realize a lifetime power supply for wireless sensor networks

Selective Resistive Sintering: A Novel Additive Manufacturing Process

Selective laser sintering (SLS) is one of the most popular 3D printing methods that uses a laser to pattern energy and selectively sinter powder particles to build 3D geometries. However, this printing method is plagued by slow printing speeds, high power consumption, difficulty to scale, and high overhead expense. In this research, a new 3D printing method is proposed to overcome these limitations of SLS. Instead of using a laser to pattern energy, this new method, termed selective resistive sintering (SRS), uses an array of microheaters to pattern heat for selectively sintering materials. Using microheaters offers significant power savings, significantly reduced overhead cost, and increased printing speed scalability. The objective of this thesis is to obtain a proof of concept of this new method. To achieve this objective, we first designed a microheater to operate at temperatures of 600⁰C, with a thermal response time of ~1 ms, and even heat distribution. A packaging device with electrical interconnects was also designed, fabricated, and assembled with necessary electrical components. Finally, a z-stage was designed to control the airgap between the printhead and the powder particles. The whole system was tested using two different scenarios. Simulations were also conducted to determine the feasibility of the printing method. We were able to successfully operate the fabricated microheater array at a power consumption of 1.1W providing significant power savings over lasers. Experimental proof of concept was unsuccessful due to the lack of precise control of the experimental conditions, but simulation results suggested that selectivity sintering nanoparticles with the microheater array was a viable process. Based on our current results that the microheater can be operated at ~1ms timescale to sinter powder particles, it is believed this new process can potentially be significantly quicker than selective laser sintering by increasing the number of microheater elements in the array. The low cost of a microheater array printhead will also make this new process affordable. This thesis presented a pioneering study on the feasibility of the proposed SRS process, which could potentially enable the development of a much more affordable and efficient alternative to SLS

LOW TEMPERATURE TENSILE TESTING OF INDEPENDENTLY FABRICATED GOLD THIN FILM SAMPLES

Tensile testing of free standing thin films is of great importance for determining their material properties. Samples have always been co fabricated with the MEMS device being used as the test apparatus. Consequently, a new device has to be used each time a new sample is tested, resulting in loss of precision. The proposed idea is to independently fabricate free standing gold thin film samples and transfer them to a separately fabricated cascaded thermal actuator setup. Thermal actuators are desirable due to the large deflections and forces they provide while maintaining a relatively low thermal gradient across the test specimen. 250 nm thick Gold samples are fabricated with varying lengths of 50,100, 500, 625 & 750 μm with corresponding thermal actuators. Also, to study the drastic effects of change in temperature on the tensile behavior of these samples, a lab scale cryostat capable of experimentation in the 4 K -300 K temperature range is also developed and presented in detail in the first half of this thesis

Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)