Telescience Testbed Pilot Program

The Telescience Testbed Pilot Program is developing initial recommendations for requirements and design approaches for the information systems of the Space Station era. During this quarter, drafting of the final reports of the various participants was initiated. Several drafts are included in this report as the University technical reports

Distributed and decentralized control in fully distributed processing systems

Issued as Quarterly progress reports no. 1-5, and Final technical report, Project no. G-36-649Final technical report has title: Distributed and decentralized control in fully distributed processing system

Research on fully distributed data processing systems

Issued as Quarterly progress reports, nos. 1-11, and Project report, Project no. G-36-64

A Comprehensive Study of DRAM Controllers in Real-Time Systems

The DRAM main memory is a critical component and a performance bottleneck of almost all computing systems. Since the DRAM is a shared memory resource on multi-core plat- forms, all cores contend for the memory bandwidth. Therefore, there is a keen interest in the real-time community to design predictable DRAM controllers to provide a low memory access latency bound to meet the strict timing requirement of real-time applications. Due to the lack of generalization of publicly available DRAM controller models in full-system and DRAM device simulators, researchers often design in-house simulator to validate their designs. An extensible cycle-accurate DRAM controller simulation frame- work is developed to simplify the process of validating new DRAM controller designs. To prove the extensibility and reusability of the framework, ten state-of-the-art predictable DRAM controllers are implemented in the framework with less than 200 lines of new code. With the help of the framework, a comprehensive evaluation of state-of-the-art pre- dictable DRAM controllers is performed analytically and experimentally to show the im- pact of different system parameters. This extensive evaluation allows researchers to assess the contribution of state-of-the-art DRAM controller approaches. At last, a novel DRAM controller with request reordering technique is proposed to provide a configurable trade-off between latency bound and bandwidth in mixed-critical systems. Compared to the state-of-the-art DRAM controller, there is a balance point between the two designs which depends on the locality of the task under analysis and the DRAM device used in the system

Parallelizing support vector machines for scalable image annotation

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Machine learning techniques have facilitated image retrieval by automatically classifying and annotating images with keywords. Among them Support Vector Machines (SVMs) are used extensively due to their generalization properties. However, SVM training is notably a computationally intensive process especially when the training dataset is large. In this thesis distributed computing paradigms have been investigated to speed up SVM training, by partitioning a large training dataset into small data chunks and process each chunk in parallel utilizing the resources of a cluster of computers. A resource aware parallel SVM algorithm is introduced for large scale image annotation in parallel using a cluster of computers. A genetic algorithm based load balancing scheme is designed to optimize the performance of the algorithm in heterogeneous computing environments. SVM was initially designed for binary classifications. However, most classification problems arising in domains such as image annotation usually involve more than two classes. A resource aware parallel multiclass SVM algorithm for large scale image annotation in parallel using a cluster of computers is introduced. The combination of classifiers leads to substantial reduction of classification error in a wide range of applications. Among them SVM ensembles with bagging is shown to outperform a single SVM in terms of classification accuracy. However, SVM ensembles training are notably a computationally intensive process especially when the number replicated samples based on bootstrapping is large. A distributed SVM ensemble algorithm for image annotation is introduced which re-samples the training data based on bootstrapping and training SVM on each sample in parallel using a cluster of computers. The above algorithms are evaluated in both experimental and simulation environments showing that the distributed SVM algorithm, distributed multiclass SVM algorithm, and distributed SVM ensemble algorithm, reduces the training time significantly while maintaining a high level of accuracy in classifications

A Composable Worst Case Latency Analysis for Multi-Rank DRAM Devices under Open Row Policy

The final publication is available at Springer via http://dx.doi.org/10.1007/s11241-016-9253-4As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predictable memory controllers to provide guaranteed memory access latency. However, the performance of such controllers sharply decreases as DDR devices become faster and the width of memory buses is increased. High-performance Commercial-Off-The-Shelf (COTS) memory controllers in general-purpose systems employ open row policy to improve average case access latencies and memory throughput, but the use of such policy is not compatible with existing real-time controllers. In this article, we present a new memory controller design together with a novel, composable worst case analysis for DDR DRAM that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state. In particular, our approach scales better with increasing memory speed by predictably taking advantage of shorter latency for access to open DRAM rows. Furthermore, it can be applied to multi-rank devices, which allow for increased access parallelism. We evaluate our approach based on worst case analysis bounds and simulation results, using both synthetic tasks and a set of realistic benchmarks. In particular, benchmark evaluations show up to 45% improvement in worst case task execution time compared to a competing predictable memory controller for a system with 16 requestors and one rank.NSERC DG || 402369-2011 CMC Microsystem

Development of a simulation backplane with dynamic configurability

The subject of this thesis was the development a simulation backplane for coupling an electrical simulator with a mechanical finite-element simulator although the backplane is applicable to any simulator with the proper architecture. To tradeoff performance and accuracy during the analysis, a dynamic configuration option was included, where different simulators and models in a simulator can be switched in and out during the analysis. This option provided the designer with the flexibility to analyze all details of simulations from different modeling representations to optimizing the simulation performance within the same analysis. This backplane was able to transverse multiple coupling architectures to be a configuration tool for simulating hybrid environments with dynamic changes. In this work, the dynamic configurability procedure was outlined with other issues and procedures for coupling multiple simulators. To improve upon the basic coupling process, different interface configurations were examined in different casualty-based formats. Specifically, conventional interface combinations were compared under different sensitivity calculation criteria and methods to find the interface or combination with the best iteration efficiency and convergence. The iteration efficiency was typically determined by the sensitivity calculation options while the convergence was determined by the interface combination between the simulators and by the backplane initialization sequence. The optimum convergence for any conventional interface combination was 93%. From these analyses, a dynamic-interface configuration procedure was developed based on coupling conditions and variable causality to identify the interface configuration with the best chances of convergence. A tiered dynamic interface procedure had convergence of 95% and equivalent iteration efficiency with the conventional interfaces. Finally, a flow correction method using behavioral models was examined, where a predictor and corrector process was implemented that allowed more versatility in the coupling process and improved initialization compared to the other interfaces. The flow correction process had a convergence of 93% tested over behavioral models with different accuracy constraints. A sensitivity calculation problem limited the success of the flow correction procedure and caused the iteration inefficiency to be two times larger than the other procedures