Energy Efficient Engine (E3) controls and accessories detail design report

An Energy Efficient Engine program has been established by NASA to develop technology for improving the energy efficiency of future commercial transport aircraft engines. As part of this program, a new turbofan engine was designed. This report describes the fuel and control system for this engine. The system design is based on many of the proven concepts and component designs used on the General Electric CF6 family of engines. One significant difference is the incorporation of digital electronic computation in place of the hydromechanical computation currently used

Spacecraft On-Board Information Extraction Computer (SOBIEC)

The Jet Propulsion Laboratory is the Technical Monitor on an SBIR Program issued for Irvine Sensors Corporation to develop a highly compact, dual use massively parallel processing node known as SOBIEC. SOBIEC couples 3D memory stacking technology provided by nCUBE. The node contains sufficient network Input/Output to implement up to an order-13 binary hypercube. The benefit of this network, is that it scales linearly as more processors are added, and it is a superset of other commonly used interconnect topologies such as: meshes, rings, toroids, and trees. In this manner, a distributed processing network can be easily devised and supported. The SOBIEC node has sufficient memory for most multi-computer applications, and also supports external memory expansion and DMA interfaces. The SOBIEC node is supported by a mature set of software development tools from nCUBE. The nCUBE operating system (OS) provides configuration and operational support for up to 8000 SOBIEC processors in an order-13 binary hypercube or any subset or partition(s) thereof. The OS is UNIX (USL SVR4) compatible, with C, C++, and FORTRAN compilers readily available. A stand-alone development system is also available to support SOBIEC test and integration

Network-on-chip design for a chiplet-based waferscale processor

Motivated by the failing of Moore’s law and Dennard scaling, as well as increasingly large parallel tasks like machine learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores

The ALICE Silicon Pixel Detector Control and Calibration Systems

The work presented in this thesis was carried out in the Silicon Pixel Detector (SPD) group of the ALICE experiment at the Large Hadron Collider (LHC). The SPD is the innermost part (two cylindrical layers of silicon pixel detec- tors) of the ALICE Inner Tracking System (ITS). During the last three years I have been strongly involved in the SPD hardware and software development, construction and commissioning. This thesis is focused on the design, development and commissioning of the SPD Control and Calibration Systems. I started this project from scratch. After a prototyping phase now a stable version of the control and calibration systems is operative. These systems allowed the detector sectors and half-barrels test, integration and commissioning as well as the SPD commissioning in the experiment. The integration of the systems with the ALICE Experiment Control System (ECS), DAQ and Trigger system has been accomplished and the SPD participated in the experimental December 2007 commissioning run. The complexity of the detectors, the high number of subcomponents and the harsh working environment make necessary the development of a control system parallel to the data acquisition. This online slow control, called Detector Control System (DCS), has the task of controlling and monitoring all hardware and software components of the detector and of the necessary infrastructures. The latter include the power distribution system, cool ing, interlock system, etc. In this scenario, the DCS assumes a key role. Its functionalities have extended well over the simple control and monitoring of the experiment. DCS, nowadays, are highly advanced and automated online data acquisition systems, with less stringent requirements compared to the DAQ. Moreover the SPD DCS has the unique feature of not only controlling but also operating the SPD front-end electronics. These requirements impose a high level of synchronization between the system components and a fast system response. The DCS, in this case, is a fundamental component for the detector calibration. The SPD DCS should be operated in the ALICE DCS framework hence a series of integration constraint should be applied to the system. Furthermore, in complex experiments such as ALICE, the detector operation is tightly bound to the connection and integration of the various systems such as DAQ, DCS, trigger system, Experiment Control System (ECS) and Offline framework. The operation of the SPD front-end electronics and services should be done at various levels of integration. At the first and bottom level it is required that each system runs safely and independently. At the second level the subsystem controls should be merged to form a unique entity. At this stage the components operation should be synchronized to reach the full detector operation. The third level requires the integration of the SPD control in the genera l ALICE DCS/ECS. These requirements have been fulfilled by designing the DCS with two main software layers. On the bottom a Supervisory Control And Data Acquisition (SCADA) layer controls and monitors the equipments. It is based on a commercial application, PVSS, and it also responsible of provide an user interface to the subsystem components. On top a Finite State Machine (FSM) Layer performs the logical connection between the SPD subsystems and it connects the SPD DCS with the ALICE DCS and ECS. PVSS is designed for slow control applications and it is not suitable for the direct control of the fast SPD front-end electronics. I designed a Front-End Device Server (FED Server) to interface the SCADA layer with the front-end electronics. The server receives macro-instructions from the SCADA and it operates autonomously the complex front-end electronics. The complexity of the detector calibration requires a high automation level and the integration of the calibration system with the ALICE calibration framework. In order to satisfy these requirements and provide the user with a simple and versatile interface, I decided to foresee two calibration scenarios. A calibration scenario, named DAQ ACTIVE, allows the fast detector calibration but it needs the control of the full detector and subsystems. A second calibration scenario, named DCS ONLY, slower than the DAQ ACTIVE scenario, allows the calibration of a detector partition without interference with the normal detector operation. The control and calibration systems have been used to characterize and test the SPD components before and after the integration in the detector, both in laboratory (DSF) and in the ALICE environment. Some calibration and control systems application examples as well as a brief overview of the detector performance evaluated during the commissioning phases are reported

Stochastic optimazation models for planning and operation of a multipurpose water reservoir

We consider the capacity determination problem of a hydro reservoir. The reservoir is to be used primarily for hydropower generation; however, commitments on release targets for irrigation as well as mitigation of downstream flood hazards are also sec-ondary objectives. This thesis is concerned with studying the complex interaction among various system reliabilities (power, flood, irrigation, etc.) and to provide de-cision makers a planning tool for further investigation. The main tools are stochastic programming models that recognize the randomness in the streamflow. A chance con-strained programming model and a stochastic programming model with recourse are formulated and solved. The models developed incorporate a special target-priority policy according to given system reliabilities. Optimized values are then used in a simulation model to investigate the system behavior. Detailed computational results are provided and analyzed

Critical Infrastructures: Enhancing Preparedness & Resilience for the Security of Citizens and Services Supply Continuity: Proceedings of the 52nd ESReDA Seminar Hosted by the Lithuanian Energy Institute & Vytautas Magnus University

Critical Infrastructures Preparedness and Resilience is a major societal security issue in modern society. Critical Infrastructures (CIs) provide vital services to modern societies. Some CIs’ disruptions may endanger the security of the citizen, the safety of the strategic assets and even the governance continuity. The European Safety, Reliability and Data Association (ESReDA) as one of the most active EU networks in the field has initiated a project group on the “Critical Infrastructure/Modelling, Simulation and Analysis – Data”. The main focus of the project group is to report on the state of progress in MS&A of the CIs preparedness & resilience with a specific focus on the corresponding data availability and relevance. In order to report on the most recent developments in the field of the CIs preparedness & resilience MS&A and the availability of the relevant data, ESReDA held its 52nd Seminar on the following thematic: “Critical Infrastructures: Enhancing Preparedness & Resilience for the security of citizens and services supply continuity”. The 52nd ESReDA Seminar was a very successful event, which attracted about 50 participants from industry, authorities, operators, research centres, academia and consultancy companies.JRC.G.10-Knowledge for Nuclear Security and Safet

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology