Circuit simulation using distributed waveform relaxation techniques

Simulation plays an important role in the design of integrated circuits. Due to high costs and large delays involved in their fabrication, simulation is commonly used to verify functionality and to predict performance before fabrication. This thesis describes analysis, implementation and performance evaluation of a distributed memory parallel waveform relaxation technique for the electrical circuit simulation of MOS VLSI circuits. The waveform relaxation technique exhibits inherent parallelism due to the partitioning of a circuit into a number of sub-circuits. These subcircuits can be concurrently simulated on parallel processors. Different forms of parallelism in the direct method and the waveform relaxation technique are studied. An analysis of single queue and distributed queue approaches to implement parallel waveform relaxation on distributed memory machines is performed and their performance implications are studied. The distributed queue approach selected for exploiting the coarse grain parallelism across sub-circuits is described. Parallel waveform relaxation programs based on Gauss-Seidel and Gauss-Jacobi techniques are implemented using a network of eight Transputers. Static and dynamic load balancing strategies are studied. A dynamic load balancing algorithm is developed and implemented. Results of parallel implementation are analyzed to identify sources of bottlenecks. This thesis has demonstrated the applicability of a low cost distributed memory multi-computer system for simulation of MOS VLSI circuits. Speed-up measurements prove that a five times improvement in the speed of calculations can be achieved using a full window parallel Gauss-Jacobi waveform relaxation algorithm. Analysis of overheads shows that load imbalance is the major source of overhead and that the fraction of the computation which must be performed sequentially is very low. Communication overhead depends on the nature of the parallel architecture and the design of communication mechanisms. The run-time environment (parallel processing framework) developed in this research exploits features of the Transputer architecture to reduce the effect of the communication overhead by effectively overlapping computation with communications, and running communications processes at a higher priority. This research will contribute to the development of low cost, high performance workstations for computer-aided design and analysis of VLSI circuits

A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications. The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum. In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect.As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25?m, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters

Enhancements of MEMS design flow for Automotive and Optoelectronic applications

In the latest years we have been witnesses of a very rapidly and amazing grown of MicroElectroMechanical systems (MEMS) which nowadays represent the outstanding state-of-the art in a wide variety of applications from automotive to commercial, biomedical and optical (MicroOptoElectroMechanicalSystems). The increasing success of MEMS is found in their high miniaturization capability, thus allowing an easy integration with electronic circuits, their low manufacturing costs (that comes directly from low unit pricing and indirectly from cutting service and maintaining costs) and low power consumption. With the always growing interest around MEMS devices the necessity arises for MEMS designers to define a MEMS design flow. Indeed it is widely accepted that in any complex engineering design process, a well defined and documented design flow or procedure is vital. The top-level goal of a MEMS/MOEMS design flow is to enable complex engineering design in the shortest time and with the lowest number of fabrication iterations, preferably only one. These two characteristics are the measures of a good flow, because they translate directly to the industry-desirable reductions of the metrics “time to market” and “costs”. Like most engineering flows, the MEMS design flow begins with the product definition that generally involves a feasibility study and the elaboration of the device specifications. Once the MEMS specifications are set, a Finite Element Method (FEM) model is developed in order to study its physical behaviour and to extract the characteristic device parameters. These latter are used to develop a high level MEMS model which is necessary to the design of the sensor read out electronics. Once the MEMS geometry is completely defined and matches the device specifications, the device layout must be generated, and finally the MEMS sensor is fabricated. In order to have a MEMS sensor working according to specifications at first production run is essential that the MEMS design flow is as close as possible to the optimum design flow. The key factors in the MEMS design flow are the development of a sensor model as close as possible to the real device and the layout realization. This research work addresses these two aspects by developing optimized custom tools (a tool for layout check (LVS) and a tool for parasitic capacitances extraction) and new methodologies (a methodology for post layout simulations) which support the designer during the crucial steps of the design process as well as by presenting the models of two cases studies belonging to leading MEMS applications (a micromirror for laser projection system and a control loop for the shock immunity enhancement in gyroscopes for automotive applications)

NASAP-70 User's and Programmer's Manual

User and programmer manual for NASAP-70 digital circuit analysis progra

Index to 1984 NASA Tech Briefs, volume 9, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1984 Tech B Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Customer premise service study for 30/20 GHz satellite system

Satellite systems in which the space segment operates in the 30/20 GHz frequency band are defined and compared as to their potential for providing various types of communications services to customer premises and the economic and technical feasibility of doing so. Technical tasks performed include: market postulation, definition of the ground segment, definition of the space segment, definition of the integrated satellite system, service costs for satellite systems, sensitivity analysis, and critical technology. Based on an analysis of market data, a sufficiently large market for services is projected so as to make the system economically viable. A large market, and hence a high capacity satellite system, is found to be necessary to minimize service costs, i.e., economy of scale is found to hold. The wide bandwidth expected to be available in the 30/20 GHz band, along with frequency reuse which further increases the effective system bandwidth, makes possible the high capacity system. Extensive ground networking is required in most systems to both connect users into the system and to interconnect Earth stations to provide spatial diversity. Earth station spatial diversity is found to be a cost effective means of compensating the large fading encountered in the 30/20 GHz operating band