247 research outputs found
Communication-Efficient Probabilistic Algorithms: Selection, Sampling, and Checking
Diese Dissertation behandelt drei grundlegende Klassen von Problemen in Big-Data-Systemen, fĂŒr die wir kommunikationseffiziente probabilistische Algorithmen entwickeln. Im ersten Teil betrachten wir verschiedene Selektionsprobleme, im zweiten Teil das Ziehen gewichteter Stichproben (Weighted Sampling) und im dritten Teil die probabilistische KorrektheitsprĂŒfung von Basisoperationen in Big-Data-Frameworks (Checking). Diese Arbeit ist durch einen wachsenden Bedarf an Kommunikationseffizienz motiviert, der daher rĂŒhrt, dass der auf das Netzwerk und seine Nutzung zurĂŒckzufĂŒhrende Anteil sowohl der Anschaffungskosten als auch des Energieverbrauchs von Supercomputern und der Laufzeit verteilter Anwendungen immer weiter wĂ€chst. Ăberraschend wenige kommunikationseffiziente Algorithmen sind fĂŒr grundlegende Big-Data-Probleme bekannt. In dieser Arbeit schlieĂen wir einige dieser LĂŒcken.
ZunĂ€chst betrachten wir verschiedene Selektionsprobleme, beginnend mit der verteilten Version des klassischen Selektionsproblems, d. h. dem Auffinden des Elements von Rang in einer groĂen verteilten Eingabe. Wir zeigen, wie dieses Problem kommunikationseffizient gelöst werden kann, ohne anzunehmen, dass die Elemente der Eingabe zufĂ€llig verteilt seien. Hierzu ersetzen wir die Methode zur Pivotwahl in einem schon lange bekannten Algorithmus und zeigen, dass dies hinreichend ist. AnschlieĂend zeigen wir, dass die Selektion aus lokal sortierten Folgen â multisequence selection â wesentlich schneller lösbar ist, wenn der genaue Rang des Ausgabeelements in einem gewissen Bereich variieren darf. Dies benutzen wir anschlieĂend, um eine verteilte PrioritĂ€tswarteschlange mit Bulk-Operationen zu konstruieren. SpĂ€ter werden wir diese verwenden, um gewichtete Stichproben aus Datenströmen zu ziehen (Reservoir Sampling). SchlieĂlich betrachten wir das Problem, die global hĂ€ufigsten Objekte sowie die, deren zugehörige Werte die gröĂten Summen ergeben, mit einem stichprobenbasierten Ansatz zu identifizieren.
Im Kapitel ĂŒber gewichtete Stichproben werden zunĂ€chst neue Konstruktionsalgorithmen fĂŒr eine klassische Datenstruktur fĂŒr dieses Problem, sogenannte Alias-Tabellen, vorgestellt. Zu Beginn stellen wir den ersten Linearzeit-Konstruktionsalgorithmus fĂŒr diese Datenstruktur vor, der mit konstant viel Zusatzspeicher auskommt. AnschlieĂend parallelisieren wir diesen Algorithmus fĂŒr Shared Memory und erhalten so den ersten parallelen Konstruktionsalgorithmus fĂŒr Aliastabellen. Hiernach zeigen wir, wie das Problem fĂŒr verteilte Systeme mit einem zweistufigen Algorithmus angegangen werden kann. AnschlieĂend stellen wir einen ausgabesensitiven Algorithmus fĂŒr gewichtete Stichproben mit ZurĂŒcklegen vor. Ausgabesensitiv bedeutet, dass die Laufzeit des Algorithmus sich auf die Anzahl der eindeutigen Elemente in der Ausgabe bezieht und nicht auf die GröĂe der Stichprobe. Dieser Algorithmus kann sowohl sequentiell als auch auf Shared-Memory-Maschinen und verteilten Systemen eingesetzt werden und ist der erste derartige Algorithmus in allen drei Kategorien. Wir passen ihn anschlieĂend an das Ziehen gewichteter Stichproben ohne ZurĂŒcklegen an, indem wir ihn mit einem SchĂ€tzer fĂŒr die Anzahl der eindeutigen Elemente in einer Stichprobe mit ZurĂŒcklegen kombinieren. Poisson-Sampling, eine Verallgemeinerung des Bernoulli-Sampling auf gewichtete Elemente, kann auf ganzzahlige Sortierung zurĂŒckgefĂŒhrt werden, und wir zeigen, wie ein bestehender Ansatz parallelisiert werden kann. FĂŒr das Sampling aus Datenströmen passen wir einen sequentiellen Algorithmus an und zeigen, wie er in einem Mini-Batch-Modell unter Verwendung unserer im Selektionskapitel eingefĂŒhrten Bulk-PrioritĂ€tswarteschlange parallelisiert werden kann. Das Kapitel endet mit einer ausfĂŒhrlichen Evaluierung unserer Aliastabellen-Konstruktionsalgorithmen, unseres ausgabesensitiven Algorithmus fĂŒr gewichtete Stichproben mit ZurĂŒcklegen und unseres Algorithmus fĂŒr gewichtetes Reservoir-Sampling.
Um die Korrektheit verteilter Algorithmen probabilistisch zu verifizieren, schlagen wir Checker fĂŒr grundlegende Operationen von Big-Data-Frameworks vor. Wir zeigen, dass die ĂberprĂŒfung zahlreicher Operationen auf zwei âKernâ-Checker reduziert werden kann, nĂ€mlich die PrĂŒfung von Aggregationen und ob eine Folge eine Permutation einer anderen Folge ist. WĂ€hrend mehrere AnsĂ€tze fĂŒr letzteres Problem seit geraumer Zeit bekannt sind und sich auch einfach parallelisieren lassen, ist unser Summenaggregations-Checker eine neuartige Anwendung der gleichen Datenstruktur, die auch zĂ€hlenden Bloom-Filtern und dem Count-Min-Sketch zugrunde liegt. Wir haben beide Checker in Thrill, einem Big-Data-Framework, implementiert. Experimente mit absichtlich herbeigefĂŒhrten Fehlern bestĂ€tigen die von unserer theoretischen Analyse vorhergesagte Erkennungsgenauigkeit. Dies gilt selbst dann, wenn wir hĂ€ufig verwendete schnelle Hash-Funktionen mit in der Theorie suboptimalen Eigenschaften verwenden. Skalierungsexperimente auf einem Supercomputer zeigen, dass unsere Checker nur sehr geringen Laufzeit-Overhead haben, welcher im Bereich von liegt und dabei die Korrektheit des Ergebnisses nahezu garantiert wird
Dependable Computing on Inexact Hardware through Anomaly Detection.
Reliability of transistors is on the decline as transistors continue to shrink in size. Aggressive voltage scaling is making the problem even worse. Scaled-down transistors are more susceptible to transient faults as well as permanent in-field hardware failures. In order to continue to reap the benefits of technology scaling, it has become imperative to tackle the challenges risen due to the decreasing reliability of devices for the mainstream commodity market. Along with the worsening reliability, achieving energy efficiency and performance improvement by scaling is increasingly providing diminishing marginal returns. More than any other time in history, the semiconductor industry faces the crossroad of unreliability and the need to improve energy efficiency.
These challenges of technology scaling can be tackled by categorizing the target applications in the following two categories: traditional applications that have relatively strict correctness requirement on outputs and emerging class of soft applications, from various domains such as multimedia, machine learning, and computer vision, that are inherently inaccuracy tolerant to a certain degree. Traditional applications can be protected against hardware failures by low-cost detection and protection methods while soft applications can trade off quality of outputs to achieve better performance or energy efficiency.
For traditional applications, I propose an efficient, software-only application analysis and transformation solution to detect data and control flow transient faults. The intelligence of the data flow solution lies in the use of dynamic application information such as control flow, memory and value profiling. The control flow protection technique achieves its efficiency by simplifying signature calculations in each basic block and by performing checking at a coarse-grain level. For soft applications, I develop a quality control technique. The quality control technique employs continuous, light-weight checkers to ensure that the approximation is controlled and application output is acceptable. Overall, I show that the use of low-cost checkers to produce dependable results on commodity systems---constructed from inexact hardware components---is efficient and practical.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113341/1/dskhudia_1.pd
Formal methods for functional verification of cache-coherent systems-on-chip
State-of-the-art System-on-Chip (SoC) architectures integrate many different components, such as processors, accelerators, memories, and I/O blocks. Some of those components, but not all, may have caches. Because the effort of validation with simulation-based techniques, currently used in industry, grows exponentially with the complexity of the SoC, this thesis investigates the use of formal verification techniques in this context. More precisely, we use the CADP toolbox to develop and validate a generic formal model of a heterogeneous cache-coherent SoC compliant with the recent AMBA 4 ACE specification proposed by ARM. We use a constraint-oriented specification style to model the general requirements of the specification. We verify system properties on both the constrained and unconstrained model to detect the cache coherency corner cases. We take advantage of the parametrization of the proposed model to produce a comprehensive set of counterexamples of non-satisfied properties in the unconstrained model. The results of formal verification are then used to improve the industrial simulation-based verification techniques in two aspects. On the one hand, we suggest using the formal model to assess the sanity of an interface verification unit. On the other hand, in order to generate clever semi-directed test cases from temporal logic properties, we propose a two-step approach. One step consists in generating system-level abstract test cases using model-based testing tools of the CADP toolbox. The other step consists in refining those tests into interface-level concrete test cases that can be executed at RTL level with a commercial Coverage-Directed Test Generation tool. We found that our approach helps in the transition between interface-level and system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench.Les architectures des systĂšmes sur puce (System-on-Chip, SoC) actuelles intĂšgrent de nombreux composants diffĂ©rents tels que les processeurs, les accĂ©lĂ©rateurs, les mĂ©moires et les blocs d'entrĂ©e/sortie, certains pouvant contenir des caches. Vu que l'effort de validation basĂ©e sur la simulation, actuellement utilisĂ©e dans l'industrie, croĂźt de façon exponentielle avec la complexitĂ© des SoCs, nous nous intĂ©ressons Ă des techniques de vĂ©rification formelle. Nous utilisons la boĂźte Ă outils CADP pour dĂ©velopper et valider un modĂšle formel d'un SoC gĂ©nĂ©rique conforme Ă la spĂ©cification AMBA 4 ACE rĂ©cemment proposĂ©e par ARM dans le but de mettre en Ćuvre la cohĂ©rence de cache au niveau systĂšme. Nous utilisons une spĂ©cification orientĂ©e contraintes pour modĂ©liser les exigences gĂ©nĂ©rales de cette spĂ©cification. Les propriĂ©tĂ©s du systĂšme sont vĂ©rifiĂ© Ă la fois sur le modĂšle avec contraintes et le modĂšle sans contraintes pour dĂ©tecter les cas intĂ©ressants pour la cohĂ©rence de cache. La paramĂ©trisation du modĂšle proposĂ© a permis de produire l'ensemble complet des contre-exemples qui ne satisfont pas une certaine propriĂ©tĂ© dans le modĂšle non contraint. Notre approche amĂ©liore les techniques industrielles de vĂ©rification basĂ©es sur la simulation en deux aspects. D'une part, nous suggĂ©rons l'utilisation du modĂšle formel pour Ă©valuer la bonne construction d'une unitĂ© de vĂ©rification d'interface. D'autre part, dans l'objectif de gĂ©nĂ©rer des cas de test semi-dirigĂ©s intelligents Ă partir des propriĂ©tĂ©s de logique temporelle, nous proposons une approche en deux Ă©tapes. La premiĂšre Ă©tape consiste Ă gĂ©nĂ©rer des cas de tests abstraits au niveau systĂšme en utilisant des outils de test basĂ© sur modĂšle de la boĂźte Ă outils CADP. La seconde Ă©tape consiste Ă affiner ces tests en cas de tests concrets au niveau de l'interface qui peuvent ĂȘtre exĂ©cutĂ©s en RTL grĂące aux services d'un outil commercial de gĂ©nĂ©ration de tests dirigĂ©s par les mesures de couverture. Nous avons constatĂ© que notre approche participe dans la transition entre la vĂ©rification du niveau interface, classiquement pratiquĂ©e dans l'industrie du matĂ©riel, et la vĂ©rification au niveau systĂšme. Notre approche facilite aussi la validation des propriĂ©tĂ©s globales du systĂšme, et permet une dĂ©tection prĂ©coce des bugs, tant dans le SoC que dans les bancs de test commerciales
A critical analysis of the relationship between business information system technology and supply chain management with special reference to optimum efficiency within large enterprises in the food and drug retail sector in KwaZulu-Natal.
Masters Degree. University of KwaZulu-Natal, Pietermaritzburg.The purpose of this research is to explore the relationship between supply chain
management and business information system technology within the food and drug
retail sector with special reference to optimum efficiency. Business information
system technology leverages information and knowledge sharing throughout the
supply chain which enables them to respond more effectively to an ever-changing
and volatile marketplace. The relationship between supply chain management and
business information system technology is multi-faceted and complex in nature, and
consequently, has the ability to penetrate every element of an organisationâs
functionality. Furthermore, it has the ability to penetrate the functionality of an
entire chain or network of suppliers and markets irrespective of their position
around the globe.
Supply Chain management literature teaches that optimisation within functional
areas is not as effective as cross-optimisation across functions and supply chain
networks. As supply chains rely on business information technology for crossoptimisation,
optimum efficiency will always be a moving target for as long as
business technology and supply chain management continue to break through new
ground.
In this research large food and drug supply chain networks and their business
information system requirements, trends, influence, effect and constraints were
reviewed, with special reference to creating optimum efficiency in their supply chain
networks. This research was motivated by discussions with Pick ân Payâs business
information systemâs service provider and their desire to optimise Pick ân Payâs
supply chain network efficiency in a highly price-competitive environment, resulting
in an in-depth case study being carried out on Pick ân Pay (Pty) Ltd stores in
KwaZulu-Natal. The review of literature suggests that cross-optimisation is only
mutually beneficial within trust relationships that exhibit seamless flows of
information throughout a supply chain. Data suggests that despite Pick ân Payâs use
of advanced business information system technology, Pick ân Pay together with the
food and drug retail stores in South Africa have a long way to go on this issue
Tools and Algorithms for the Construction and Analysis of Systems
This open access two-volume set constitutes the proceedings of the 27th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2021, which was held during March 27 â April 1, 2021, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2021. The conference was planned to take place in Luxembourg and changed to an online format due to the COVID-19 pandemic. The total of 41 full papers presented in the proceedings was carefully reviewed and selected from 141 submissions. The volume also contains 7 tool papers; 6 Tool Demo papers, 9 SV-Comp Competition Papers. The papers are organized in topical sections as follows: Part I: Game Theory; SMT Verification; Probabilities; Timed Systems; Neural Networks; Analysis of Network Communication. Part II: Verification Techniques (not SMT); Case Studies; Proof Generation/Validation; Tool Papers; Tool Demo Papers; SV-Comp Tool Competition Papers
Context-driven methodologies for context-aware and adaptive systems
Applications which are both context-aware and adapting, enhance usersâ experience by anticipating their
need in relation with their environment and adapt their behavior according to environmental changes.
Being by definition both context-aware and adaptive these applications suffer both from faults related to
their context-awareness and to their adaptive nature plus from a novel variety of faults originated by the
combination of the two. This research work analyzes, classifies, detects, and reports faults belonging
to this novel class aiming to improve the robustness of these Context-Aware Adaptive Applications
(CAAAs).
To better understand the peculiar dynamics driving the CAAAs adaptation mechanism a general
high-level architectural model has been designed. This architectural model clearly depicts the stream of
information coming from sensors and being computed all the way to the adaptation mechanism. The
model identifies a stack of common components representing increasing abstractions of the context and
their general interconnections. Known faults involving context data can be re-examined according to this
architecture and can be classified in terms of the component in which they are happening and in terms
of their abstraction from the environment. Resulting from this classification is a CAAA-oriented fault
taxonomy.
Our architectural model also underlines that there is a common evolutionary path for CAAAs and
shows the importance of the adaptation logic. Indeed most of the adaptation failures are caused by
invalid interpretations of the context by the adaptation logic. To prevent such faults we defined a model,
the Adaptation Finite-State Machine (A-FSM), describing how the application adapts in response to
changes in the context. The A-FSM model is a powerful instrument which allows developers to focus in
those context-aware and adaptive aspects in which faults reside.
In this model we have identified a set of patterns of faults representing the most common faults in
this application domain. Such faults are represented as violation of given properties in the A-FSM. We
have created four techniques to detect such faults. Our proposed algorithms are based on three different
technologies: enumerative, symbolic and goal planning. Such techniques compensate each other. We
have evaluated them by comparing them to each other using both crafted models and models extracted
from existing commercial and free applications. In the evaluation we observe the validity, the readability
of the reported faults, the scalability and their behavior in limited memory environments. We conclude
this Thesis by suggesting possible extensions
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