754 research outputs found
Data dependent energy modelling for worst case energy consumption analysis
Safely meeting Worst Case Energy Consumption (WCEC) criteria requires
accurate energy modeling of software. We investigate the impact of instruction
operand values upon energy consumption in cacheless embedded processors.
Existing instruction-level energy models typically use measurements from random
input data, providing estimates unsuitable for safe WCEC analysis.
We examine probabilistic energy distributions of instructions and propose a
model for composing instruction sequences using distributions, enabling WCEC
analysis on program basic blocks. The worst case is predicted with statistical
analysis. Further, we verify that the energy of embedded benchmarks can be
characterised as a distribution, and compare our proposed technique with other
methods of estimating energy consumption
Automated Exploration of the ASIC Design Space for Minimum Power-Delay-Area Product at the Register Transfer Level
Exploring the integrated circuit design space for minimum power-delay-area (PDA) product can be time-consuming and tedious, especially when the target standard-cell library has hundreds of options. In this dissertation, heuristic algorithms that automate this process have been developed, implemented and validated at the reg- ister transfer level. In some cases, the PDA product was 1.9 times better than the initial baseline solution. The parallel search algorithm exhibited 9x speed up when executed on 10 machines simultaneously. These two new methods also characterize the design space for the given RTL code by generating power-delay-area points in addition to the minimum PDA point in case the designer wishes to select a different solution that is a tradeoff among these metrics. As a final step, these two search algorithms are integrated into a fully automated ASIC design flow
Hyperspectral Unmixing on Multicore DSPs: Trading Off Performance for Energy
Wider coverage of observation missions will increase
onboard power restrictions while, at the same time, pose higher
demands from the perspective of processing time, thus asking for
the exploration of novel high-performance and low-power processing
architectures. In this paper, we analyze the acceleration
of spectral unmixing, a key technique to process hyperspectral
images, on multicore architectures. To meet onboard processing
restrictions, we employ a low-power Digital Signal Processor
(DSP), comparing processing time and energy consumption with
those of a representative set of commodity architectures. We
demonstrate that DSPs offer a fair balance between ease of
programming, performance, and energy consumption, resulting
in a highly appealing platform to meet the restrictions of current
missions if onboard processing is required
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