121 research outputs found

    Deterministic 1-k routing on meshes with applications to worm-hole routing

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    In 11-kk routing each of the n2n^2 processing units of an n×nn \times n mesh connected computer initially holds 11 packet which must be routed such that any processor is the destination of at most kk packets. This problem reflects practical desire for routing better than the popular routing of permutations. 11-kk routing also has implications for hot-potato worm-hole routing, which is of great importance for real world systems. We present a near-optimal deterministic algorithm running in \sqrt{k} \cdot n / 2 + \go{n} steps. We give a second algorithm with slightly worse routing time but working queue size three. Applying this algorithm considerably reduces the routing time of hot-potato worm-hole routing. Non-trivial extensions are given to the general ll-kk routing problem and for routing on higher dimensional meshes. Finally we show that kk-kk routing can be performed in \go{k \cdot n} steps with working queue size four. Hereby the hot-potato worm-hole routing problem can be solved in \go{k^{3/2} \cdot n} steps

    Optimal Permutation Routing for Low-dimensional Hypercubes

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    We consider the offline problem of routing a permutation of tokens on the nodes of a d-dimensional hypercube, under a queueless MIMD communication model (under the constraints that each hypercube edge may only communicate one token per communication step, and each node may only be occupied by a single token between communication steps). For a d-dimensional hypercube, it is easy to see that d communication steps are necessary. We develop a theory of “separability ” which enables an analytical proof that d steps suffice for the case d = 3, and facilitates an experimental verification that d steps suffice for d = 4. This result improves the upper bound for the number of communication steps required to route an arbitrary permutation on arbitrarily large hypercubes to 2d − 4. We also find an interesting side-result, that the number of possible communication steps in a d-dimensional hypercube is the same as the number of perfect matchings in a (d + 1)-dimensional hypercube, a combinatorial quantity for which there is no closed-form expression. Finally we present some experimental observations which may lead to a proof of a more general result for arbitrarily large dimension d. 2

    Progress Report : 1991 - 1994

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    Analysis of algorithms for online routing and scheduling in networks

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    We study situations in which an algorithm must make decisions about how to best route and schedule data transfer requests in a communication network before each transfer leaves its source. For some situations, such as those requiring quality of service guarantees, this is essential. For other situations, doing work in advance can simplify decisions in transit and increase the speed of the network. In order to reflect realistic scenarios, we require that our algorithms be online, or make their decisions without knowing future requests. We measure the efficiency of an online algorithm by its competitive ratio, which is the maximum ratio, over all request sequences, of the cost of the online algorithm\u27s solution to that of an optimal solution constructed by knowing all the requests in advance.;We identify and study two distinct variations of this general problem. In the first, data transfer requests are permanent virtual circuit requests in a circuit-switched network and the goal is to minimize the network congestion caused by the route assignment. In the second variation, data transfer requests are packets in a packet-switched network and the goal is to minimize the makespan of the schedule, or the time that the last packet reaches its destination. We present new lower bounds on the competitive ratio of any online algorithm with respect to both network congestion and makespan.;We consider two greedy online algorithms for permanent virtual circuit routing on arbitrary networks with unit capacity links, and prove both lower and upper bounds on their competitive ratios. While these greedy algorithms are not optimal, they can be expected to perform well in many circumstances and require less time to make a decision, when compared to a previously discovered asymptotically optimal online algorithm. For the online packet routing and scheduling problem, we consider an algorithm which simply assigns to each packet a priority based upon its arrival time. No packet is delayed by another packet with a lower priority. We analyze the competitive ratio of this algorithm on linear array, tree, and ring networks

    (ℓ,k)(\ell,k)-Routing on Plane Grids

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    The packet routing problem plays an essential role in communication networks. It involves how to transfer data from some origins to some destinations within a reasonable amount of time. In the (ℓ,k)(\ell,k)-routing problem, each node can send at most ℓ\ell packets and receive at most kk packets. Permutation routing is the particular case ℓ=k=1\ell=k=1. In the rr-central routing problem, all nodes at distance at most rr from a fixed node vv want to send a packet to vv. In this article we study the permutation routing, the rr-central routing and the general (ℓ,k)(\ell,k)-routing problems on plane grids, that is square grids, triangular grids and hexagonal grids. We use the \emph{store-and-forward} Δ\Delta-port model, and we consider both full and half-duplex networks. The main contributions are the following: \begin{itemize} \item[1.] Tight permutation routing algorithms on full-duplex hexagonal grids, and half duplex triangular and hexagonal grids. \item[2.] Tight rr-central routing algorithms on triangular and hexagonal grids. \item[3.] Tight (k,k)(k,k)-routing algorithms on square, triangular and hexagonal grids. \item[4.] Good approximation algorithms (in terms of running time) for (ℓ,k)(\ell,k)-routing on square, triangular and hexagonal grids, together with new lower bounds on the running time of any algorithm using shortest path routing. \end{itemize} \noindent All these algorithms are completely distributed, i.e. can be implemented independently at each node. Finally, we also formulate the (ℓ,k)(\ell,k)-routing problem as a \textsc{Weighted Edge Coloring} problem on bipartite graphs

    Complexity and Criticality in financial markets: systemic risk across frequencies and cross sections

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    Extreme market events and systemic collapses cause most of the popular attention to finance and financial markets. Extreme phenomena and the dynamics of con- nected/interacting systems have been the subject of financial modeling since early derivatives modeling, exposure risk modeling and portfolio construction. In the present work we discuss how traditional methods have for the most part failed to properly model the interconnected global financial and economic system. This led to systemic risk events and simplistic regulation which does not properly account for its implications. Analogously, we discuss how from as early as Mandelbrot’s works on financial prices and fat tails, academics, practitioners and regulators alike were warned of fat tails in financial modeling and in particular market making and derivatives pricing. The improper modeling or dismissal of these lies at the cen- tre of financial downturns ranging from LTCM’s collapse to the quant downturn of August 2007. The solution I promote in this thesis is that of complexity and criticality. In line with this we propose two lines of work. The former analyses markets as complex networks and their structure through to practical takeaways including a proof of concept for portfolio construction. The latter instead focuses on extreme events in high frequency markets with results for both tail modeling and systemic events and practical insights from those. Recent events have shown how retail investors and their savings are now heavily involved in financial markets. We hope that our contribution of methods of practical use for proper risk modeling will encourage their adoption by practitioners and regulators with the outcome of a more stable and efficient financial system

    Network-on-Chip

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    Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
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