Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology

Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation

An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

A wireless biomedical telemetry system is a device that collects biomedical signal measurements and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedical devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable device. The focus of this work is on development of an electronic front-end for wireless powering of an implantable biomedical device. The energy harvesting front-end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front-end circuit is developed in 0.13um CMOS technology with careful attention to analog layout issues. Post-layout simulation results are presented for each sub-block as well as the full front-end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5uA The complete power receiver front-end has a power conversion efficiency of up to 29%

Bandgap Reference Design at the 14-Nanometer FinFET Node

As supply voltages continue to decrease, it becomes harder to ensure that the voltage drop across a diode-connected BJT is sufficient to conduct current without sacrificing die area. One such solution to this potential problem is the diode-connected MOSFET operating in weak inversion. In addition to conducting appreciable current at voltages significantly lower than the power supply, the diode-connected MOSFET reduces the total area for the bandgap implementation. Reference voltage variations across Monte Carlo perturbations are more pronounced as the variation of process parameters are exponentially affected in subthreshold conduction. In order for this proposed solution to be feasible, a design methodology was introduced to mitigate the effects of process variation. A 14 nm bandgap reference was created and simulated across Monte Carlo perturbations for 100 runs at nominal supply voltage and 10% variation of the power supply in either direction. The best case reference voltage was found and used to verify the proposed resistive network solution. The average temperature coefficient was measured to be 66.46 ppm/◦C and the voltage adjustment range was found to be 204.1 mV. The two FinFET subthreshold diodes consume approximately 2.8% of the area of the BJT diode equivalent. Utilizing an appropriate process control technique, subthreshold bandgap references have the potential to overtake traditional BJT-based bandgap architectures in low-power, limited-area applications

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

A Sub-kT/q Voltage Reference Operating at 150 mV

We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger than 4kT/q. The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for VDD ranging from 0.15 to 1.8 V is 359.5 μV/V, whereas the mean variation of VREF in the temperature range from 0°C to 120°C is 26.74 μV/°C. The mean power consumption at 25 °C for VDD = 0.15 V is 26.1 pW. The occupied area is 1200 μm2

Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current

The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-&kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-&kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing, DC biasing, and the design of current mirrors and differential amplifiers. They attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional (non-high-&kappa/metal gate) ultra-thin oxide CMOS technologies. They require only ultra-thin oxide devices and are investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. A sub-1 V bandgap voltage reference that requires only ultra-thin oxide MOSFETs is presented (TC = 251.0 ppm/°C). It utilizes the developed methodology and illustrates that it is capable of suppressing the negative effects of direct tunneling. Its performance is compared to a thick-oxide voltage reference as a means of demonstrating that ultra-thin oxide MOSFETs can be used to build the analog component of a mixed-signal system

A Low Power Integrated Circuit for Implantable Biosensor Incorporating an On-Chip FSK Modulator

Medical care has been significantly improved in recent years due to tremendous technological advancement in the field of CMOS technology. Among those improvements, integrated circuit design and sensing techniques have brought to the doctors more flexibility and accuracy of examinations of their patients. For example, a diabetic patient needs to visit a hospital on a regular basis for the examination and proper treatment. However, with the tremendous advancement in electronic technology, a patient can soon monitor his or her own blood glucose level at home or at office with an implantable sensor which can also trigger insulin pump attached to the body. The insulin delivery system can be precisely controlled by the electronics embedded in the implantable device. In this thesis, a low power integrated circuit for the implantable biosensor incorporating an on-chip FSK modulator is presented. This design has been fabricated using AMI 0.5-μm CMOS process available through MOSIS. The simulation and test results are also presented to verify its operation

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature