247 research outputs found
Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier
This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 ”m CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator
Operational transconductance amplifier-based nonlinear function syntheses
It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirme
Fully CMOS Memristor Based Chaotic Circuit
This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 ”m process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications
Electronically Tunable Current-Mode Third-Order Square-Root-Domain Filter Design
In this study, electronically-tunable, current-mode, square-root-domain, third-order low-pass filter is proposed. The study is carried out with three circuit designs. First circuit is third-order low-pass Butterworth filter, second circuit is third-order low-pass Chebyshev filter and the last circuit is third-order low-pass elliptic filter. All the input and output values of the filter circuit are current. Only grounded capacitors and MOSFETs are required in order to realize the filter circuit. Additionally, natural frequency f0 of the current-mode filter can be adjusted electronically using outer current sources. To validate the theory and to demonstrate the performance of third-order filter, frequency and time domain simulations of PSPICE program are used. To that end, TSMC 0.35Όm Level 3 CMOS process parameters are utilized to realize the simulations of the filter. © 2018 World Scientific Publishing Company
1.5-V CMOS Current Multiplier/Divider
A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz
An Investigation into Neuromorphic ICs using Memristor-CMOS Hybrid Circuits
The memristance of a memristor depends on the amount of charge flowing
through it and when current stops flowing through it, it remembers the state.
Thus, memristors are extremely suited for implementation of memory units.
Memristors find great application in neuromorphic circuits as it is possible to
couple memory and processing, compared to traditional Von-Neumann digital
architectures where memory and processing are separate. Neural networks have a
layered structure where information passes from one layer to another and each
of these layers have the possibility of a high degree of parallelism.
CMOS-Memristor based neural network accelerators provide a method of speeding
up neural networks by making use of this parallelism and analog computation. In
this project we have conducted an initial investigation into the current state
of the art implementation of memristor based programming circuits. Various
memristor programming circuits and basic neuromorphic circuits have been
simulated. The next phase of our project revolved around designing basic
building blocks which can be used to design neural networks. A memristor bridge
based synaptic weighting block, a operational transconductor based summing
block were initially designed. We then designed activation function blocks
which are used to introduce controlled non-linearity. Blocks for a basic
rectified linear unit and a novel implementation for tan-hyperbolic function
have been proposed. An artificial neural network has been designed using these
blocks to validate and test their performance. We have also used these
fundamental blocks to design basic layers of Convolutional Neural Networks.
Convolutional Neural Networks are heavily used in image processing
applications. The core convolutional block has been designed and it has been
used as an image processing kernel to test its performance.Comment: Bachelor's thesi
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