Biomedical Engineering

Biomedical engineering is currently relatively wide scientific area which has been constantly bringing innovations with an objective to support and improve all areas of medicine such as therapy, diagnostics and rehabilitation. It holds a strong position also in natural and biological sciences. In the terms of application, biomedical engineering is present at almost all technical universities where some of them are targeted for the research and development in this area. The presented book brings chosen outputs and results of research and development tasks, often supported by important world or European framework programs or grant agencies. The knowledge and findings from the area of biomaterials, bioelectronics, bioinformatics, biomedical devices and tools or computer support in the processes of diagnostics and therapy are defined in a way that they bring both basic information to a reader and also specific outputs with a possible further use in research and development

Circuitry for a remotely powered bio-implantable gastric electrical stimulation system

Power to bio-implantable devices is usually supplied through a battery implanted with the system or through wires extending to an outside power source. The latter case with wires protruding out of the body can be unaesthetic in appearance and can cause infection. In this research, we consider an alternative way to power a bio-implantable microsystem. It involves using rechargeable lithium batteries. Here, power is delivered remotely to charge implanted battery or batteries. This approach avoids periodic surgery necessary for battery replacement. It also does not tie a person to an external power source at all times. This improves patient’s quality of life. The present work involves design and fabrication of signal conditioning circuit for a remotely rechargeable, bio-implantable, Battery-powered Electrical Stimulation System (BESS). A rechargeable lithium ion battery with a voltage of 3.7 V powers the proposed circuit. The desired output, which goes directly to the electrodes, is a series of 10 V, 15 mA pulses with a duty cycle of 4.5 %. A second rechargeable lithium ion battery serves as back-up. A lithium ion charging chip is included which is connected to the designed IC through a logic interface. The two batteries work in tandem i.e. when one battery powers the IC the other gets recharged and vice versa thereby providing an uninterruptible output. The IC uses a series of charge pumps to get the required boost in voltage. The IC also includes voltage detector circuits to detect battery voltages, voltage regulator, pulse generator circuits, logic circuits and necessary switches. Individual subsystems of the IC were designed, simulated and fabricated using standard CMOS technology. Individual subsystem circuits were found to work satisfactorily except for the charge pump. A revised design is now under fabrication. The microsystem utilizes a hybrid approach. Experiments done with a bench-top circuit model to simulate the proposed IC showed that a 3 V battery with a capacity of 190 mAh could power the IC for 15 hrs and needed 4 hrs for recharging

Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications

Communication and energy delivery architectures for personal medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 219-232).Advances in sensor technologies and integrated electronics are revolutionizing how humans access and receive healthcare. However, many envisioned wearable or implantable systems are not deployable in practice due to high energy consumption and anatomically-limited size constraints, necessitating large form-factors for external devices, or eventual surgical re-implantation procedures for in-vivo applications. Since communication and energy-management sub-systems often dominate the power budgets of personal biomedical devices, this thesis explores alternative usecases, system architectures, and circuit solutions to reduce their energy burden. For wearable applications, a system-on-chip is designed that both communicates and delivers power over an eTextiles network. The transmitter and receiver front-ends are at least an order of magnitude more efficient than conventional body-area networks. For implantable applications, two separate systems are proposed that avoid reimplantation requirements. The first system extracts energy from the endocochlear potential, an electrochemical gradient found naturally within the inner-ear of mammals, in order to power a wireless sensor. Since extractable energy levels are limited, novel sensing, communication, and energy management solutions are proposed that leverage duty-cycling to achieve enabling power consumptions that are at least an order of magnitude lower than previous work. Clinical measurements show the first system demonstrated to sustain itself with a mammalian-generated electrochemical potential operating as the only source of energy into the system. The second system leverages the essentially unlimited number of re-charge cycles offered by ultracapacitors. To ease patient usability, a rapid wireless capacitor charging architecture is proposed that employs a multi-tapped secondary inductive coil to provide charging times that are significantly faster than conventional approaches.by Patrick Philip Mercier.Ph.D