Copper Metal for Semiconductor Interconnects

Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well

Interaction between plasma and low-k dielectric materials

textWith the scaling of devices, integration of porous ultra low-κ dielectric materials into Cu interconnect becomes necessary. Low-k dielectric materials usually consist of a certain number of methyl groups and pores incorporated into a SiO₂ backbone structure to reduce the dielectric constant. They are frequently exposed to various plasmas, since plasma is widely used in VLSI semiconductor fabrication such as etching, ashing and deposition. This dissertation is aimed at exploring the interaction between plasma and low-κ dielectric surfaces. First, plasma assisted the atomic layer deposition (ALD) of Ta-based Cu barriers. Atomic layer deposition of Ta barriers is a self-limited surface reaction, determined by the function groups on the low-κ dielectric surface. But it was found TaCl₅ precursor could not nucleate on the organosilicate low-κ surface that was terminated with methyl groups. Radical NH[subscript x] beam, generated by a microwave plasma source, could activate the surface through exchanging with the methyl groups on the low-κ surface and providing active Si-NH[subscript x] nucleation sites for TaCl₅ precursors. Results from Monte Carlo simulation of the atomic layer deposition demonstrated that substrate chemistry was critical in controlling the film morphology. Second, the properties of low-κ dielectric materials tended to degrade under plasma exposure. In this dissertation, plasma damage of low-κ dielectric surface was investigated from a mechanistic point of view. Both carbon depletion and surface densification were observed on the top surface of damaged low-κ materials while the bulk remained largely uninfluenced. Plasma damage was found to be a complicated phenomenon involving both chemical and physical effects, depending on chemical reactivity and the energy and mass of the plasma species. With a downstream plasma source capable of separating ions from the plasma beam and an in-situ x-ray photoelectron spectroscopy (XPS) monitoring of the damage process, it was clear that ions played a more important role in the plasma damage process. Increase of dielectric constant after plasma damage was mainly attributed to moisture uptake and was confirmed with quantum chemistry calculation. Annealing was found to be effective in mitigating moisture uptake and thus restoring κ value. Finally, oxygen plasma damage to blanket and patterned low-κ dielectrics was studied in detail. Energetic ions in oxygen plasma contributed much to the loss of film hydrophobicity and dielectric constant through the formation of C=O and Si-OH. Based on results from residual gas analyses (RGA), three possible reaction paths leading to carbon depletion were proposed. This was followed by analytical solution of the evolution of carbon concentration during O₂ plasma damage. O₂ plasma damage to patterned CDO film was studied by TEM/EELS. And the damage behavior was simulated with Monte Carlo method. It was found that the charging potential distribution induced by plasma was important in determining the carbon loss in patterned low-k films. The charging potential distribution was mainly related to the geometry of low-k trench structures. To recover the dielectric constant, several recovery techniques were tried and briefly discussed.Physic

Beam lead technology

Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.Ph.D.Committee Chair: Kohl, Paul A.; Committee Co-Chair: Allen, Sue Ann Bidstrup; Committee Member: Carter, W. Brent; Committee Member: Frazier, Albert B; Committee Member: Hess, Dennis; Committee Member: Meredith, Carso

Low pressure chemical vapor deposition of boron nitride thin films from triethylamine borane complex and ammonia

Boron nitride thin films were synthesized on Silicon and quartz substrates by low pressure chemical vapor deposition using triethylamine-borane complex and ammonia as precursors. The films were processed at 550°C, 575°C and 600°C at a constant pressure of 0.05 Torr at different precursor flow rates and flow ratios. Several analytical methods such as Fourier transform infrared spectroscopy, x- ray photo-electron spectroscopy, ultra-violet/visible spectrophotornetry, ellipsometry, surface profilometry and scanning electron microscopy were used to study the deposited films. The films deposited were uniform, amorphous and the composition of the films varied with deposition temperature and precursor flow ratios. The stresses in the film were either mildly tensile or compressive. Dielectric constant characterization of LPCVD boron nitride was made using metal-insulator-semiconductor (MIS) and metal-insulator-metal (M IM) structures. The boron nitride films were stable and showed dielectric constant values between 3.8 and 4.7. The limitation of attaining lower values could be due to the presence of carbon as an impurity in the film and the presence of mobile charge carriers in the films as well as at the substrate-film interface

Chemical Vapor Deposition of Thin Film Materials for Copper Interconnects in Microelectronics

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate $(MnSi_xO_y)$ layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These $(MnSi_xO_y)$ layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride $(Mn_4N)$ layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the $Mn_4N$ layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. $Mn_4N$ is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process.Chemistry and Chemical Biolog

The Journal of Microelectronic Research 2005

https://scholarworks.rit.edu/meec_archive/1014/thumbnail.jp

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Conference of Microelectronics Research 2000

https://scholarworks.rit.edu/meec_archive/1009/thumbnail.jp