2,043 research outputs found
Free Speech and Its Relation to Self-Government by Alexander Meiklejohn
In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters. To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ while consuming 6.8 mW. Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR. Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist. Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2
Capacitance-to-Digital Converter for Ultra-Low-Power Wireless Sensor Nodes
Power consumption is one of the main design constraints in today’s integrated circuits. For systems like wearable electronics, UAVs, IOT systems powered by batteries which are charged using the energy harvested from various sources like RF, Thermal, Solar and Vibration, ultra-low power consumption is paramount. In these systems, Transducers which convert physical parameters into electrical parameters and the analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power signal Front End used in several low power electronic systems in general and pressure measurement systems in particular.
In this thesis, Capacitance to Digital Converter based pressure measurement system has been implemented. Here we present a general-purpose, wide-range CDC that combines a correlated double sampling (CDS) approach with a differential asynchronous SAR ADC. Since the sensor capacitor is sampled only twice per conversion, energy per conversion is low. Furthermore, since the CDS separates the sensor capacitor from the CDAC, a full differential input voltage range is preserved. The CDC has a 2.5-to-75.5pF conversion range. Monotonic SAR ADC was designed in 180nm CMOS with 1-V power supply and a 1-kS/s sampling rate with switching energy of about 100nW
An 8-Bit Analog-to-Digital Converter for Battery Operated Wireless Sensor Nodes
Wireless sensing networks (WSNs) collect analog information transduced into the form of a voltage or current. This data is typically converted into a digital representation of the value and transmitted wirelessly using various modulation techniques. As the available power and size is limited for wireless sensor nodes in many applications, a medium resolution Analog-to-Digital Converter (ADC) is proposed to convert a sensed voltage with moderate speeds to lower power consumption. Specifications also include a rail-to-rail input range and minimized errors associated with offset, gain, differential nonlinearity, and integral nonlinearity. To achieve these specifications, an 8-bit successive approximation register ADC is developed which has a conversion time of nine clock cycles. This ADC features a charge scaling array included to achieve minimized power consumption and area by reducing unit capacitance in the digital-to-analog converter. Furthermore, a latched comparator provides fast decisions utilizing positive feedback. The ADC was designed and simulated using Cadence Virtuoso with parasitic extraction over expected operating temperature range of 0 – 85°C. The design was fabricated using TSMC’s 65 nanometer RF GP process and tested on a printed circuit board to verify design specifications. The measured results for the device show an offset and gain error of +7 LSB and 31.1 LSB, respectively, and a DNL range of -0.9 LSB to +0.8 LSB and an INL range of approximately -4.6 LSB to +12 LSB. The INL is much improved in regard to the application of the temperature sensor. The INL for this region of interest is from -3.5 LSB to +2.8 LSB
ACE16K: A 128×128 focal plane analog processor with digital I/O
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The chip has been designed to achieve the high-speed and moderate-accuracy (8b) requirements of most real time early-vision processing applications. It is easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 90% of them working in analog mode, and exhibits a relatively low power consumption-<4 W, i.e. less than 1 μW per transistor. Computing vs. power peak values are in the order of 1 TeraOPS/W, while maintained VGA processing throughputs of 100 frames/s are possible with about 10-20 basic image processing tasks on each frame
A Low Power Mid-Rail Dual Slope Analog-To-Digital Converter for Biomedical Instrumentation
There are an estimated 15 million babies born preterm every year and it is on the rise. The complications that arise from this can be quite severe and are the leading causes of death among children under 5 years of age. Among these complications is a condition known as apnea. This disorder is defined as the suspension of breathing during sleep for usually 10 to 30 seconds and can occur up to 20-30 times per hour for preterm infants. This lack of oxygen in the bloodstream can have troubling effects, such as brain damage and death if the apnea period is longer than expected. This creates a dire need to continuously monitor the respiration state of babies born prematurely. Given that the breathing signal is in analog form, a conversion to its digital counterpart is necessary.In this thesis, a novel low power analog-to-digital converter (ADC) for the digitization and analyzation of the respiration signal is presented. The design of the ADC demonstrates an innovative approach on how to operate on a single polarity supply system, which effectively doubles the sampling speed. The ADC has been realized in a standard 130 nm CMOS process
Triaxial digital fluxgate magnetometer for NASA applications explorer mission: Results of tests of critical elements
Tests performed to prove the critical elements of the triaxial digital fluxgate magnetometer design were described. A method for improving the linearity of the analog to digital converter portion of the instrument was studied in detail. A sawtooth waveform was added to the signal being measured before the A/D conversion, and averaging the digital readings over one cycle of the sawtooth. It was intended to reduce bit error nonlinearities present in the A/D converter which could be expected to be as much as 16 gamma if not reduced. No such nonlinearities were detected in the output of the instrument which included the feature designed to reduce these nonlinearities. However, a small scale nonlinearity of plus or minus 2 gamma with a 64 gamma repetition rate was observed in the unit tested. A design improvement intended to eliminate this small scale nonlinearity was examined
Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter
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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system
In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration
Digital servo control of random sound test excitation
A digital servocontrol system for random noise excitation of a test object in a reverberant acoustic chamber employs a plurality of sensors spaced in the sound field to produce signals in separate channels which are decorrelated and averaged. The average signal is divided into a plurality of adjacent frequency bands cyclically sampled by a time division multiplex system, converted into digital form, and compared to a predetermined spectrum value stored in digital form. The results of the comparisons are used to control a time-shared up-down counter to develop gain control signals for the respective frequency bands in the spectrum of random sound energy picked up by the microphones
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