Age-Acknowledging Reliable Multiplier Design with Adaptive Hold Logic

Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit

MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining

Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performance and energy efficiency. In practice, the convolutions of each CNN layer are mapped to a matrix multiplication that includes all input features and kernels of each layer and is computed using a systolic array. In this work, we focus on the design of a systolic array with configurable pipeline with the goal to select an optimal pipeline configuration for each CNN layer. The proposed systolic array, called ArrayFlex, can operate in normal, or in shallow pipeline mode, thus balancing the execution time in cycles and the operating clock frequency. By selecting the appropriate pipeline configuration per CNN layer, ArrayFlex reduces the inference latency of state-of-the-art CNNs by 11%, on average, as compared to a traditional fixed-pipeline systolic array. Most importantly, this result is achieved while using 13%-23% less power, for the same applications, thus offering a combined energy-delay-product efficiency between 1.4x and 1.8x.Comment: DATE 202

Power-Aware Design Methodologies for FPGA-Based Implementation of Video Processing Systems

The increasing capacity and capabilities of FPGA devices in recent years provide an attractive option for performance-hungry applications in the image and video processing domain. FPGA devices are often used as implementation platforms for image and video processing algorithms for real-time applications due to their programmable structure that can exploit inherent spatial and temporal parallelism. While performance and area remain as two main design criteria, power consumption has become an important design goal especially for mobile devices. Reduction in power consumption can be achieved by reducing the supply voltage, capacitances, clock frequency and switching activities in a circuit. Switching activities can be reduced by architectural optimization of the processing cores such as adders, multipliers, multiply and accumulators (MACS), etc. This dissertation research focuses on reducing the switching activities in digital circuits by considering data dependencies in bit level, word level and block level neighborhoods in a video frame. The bit level data neighborhood dependency consideration for power reduction is illustrated in the design of pipelined array, Booth and log-based multipliers. For an array multiplier, operands of the multipliers are partitioned into higher and lower parts so that the probability of the higher order parts being zero or one increases. The gating technique for the pipelined approach deactivates part(s) of the multiplier when the above special values are detected. For the Booth multiplier, the partitioning and gating technique is integrated into the Booth recoding scheme. In addition, a delay correction strategy is developed for the Booth multiplier to reduce the switching activities of the sign extension part in the partial products. A novel architecture design for the computation of log and inverse-log functions for the reduction of power consumption in arithmetic circuits is also presented. This also utilizes the proposed partitioning and gating technique for further dynamic power reduction by reducing the switching activities. The word level and block level data dependencies for reducing the dynamic power consumption are illustrated by presenting the design of a 2-D convolution architecture. Here the similarities of the neighboring pixels in window-based operations of image and video processing algorithms are considered for reduced switching activities. A partitioning and detection mechanism is developed to deactivate the parallel architecture for window-based operations if higher order parts of the pixel values are the same. A neighborhood dependent approach (NDA) is incorporated with different window buffering schemes. Consideration of the symmetry property in filter kernels is also applied with the NDA method for further reduction of switching activities. The proposed design methodologies are implemented and evaluated in a FPGA environment. It is observed that the dynamic power consumption in FPGA-based circuit implementations is significantly reduced in bit level, data level and block level architectures when compared to state-of-the-art design techniques. A specific application for the design of a real-time video processing system incorporating the proposed design methodologies for low power consumption is also presented. An image enhancement application is considered and the proposed partitioning and gating, and NDA methods are utilized in the design of the enhancement system. Experimental results show that the proposed multi-level power aware methodology achieves considerable power reduction. Research work is progressing In utilizing the data dependencies in subsequent frames in a video stream for the reduction of circuit switching activities and thereby the dynamic power consumption

DESIGN OF AN EFFICIENT GETTING OLDER-AWARE NONTOXIC MULTIPLIER

An identical phenomenon, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both effects degrade transistor speed, as well as in the lengthy term, the machine may fail because of timing violations. Digital multipliers are some of the most important arithmetic functional models. The general performance of those systems is dependent around the throughput from the multiplier. Meanwhile, the negative bias temperature instability effect happens whenever a pMOS transistor is under negative bias, growing the brink current from the pMOS transistor, and reducing multiplier speed. Therefore, you should design reliable high-performance multipliers. Within this paper, we advise a maturing-aware multiplier design having a novel adaptive hold logic circuit. The multiplier has the capacity to provide greater throughput with the variable latency and may adjust the AHL circuit to mitigate performance degradation that is a result of the maturing effect. Furthermore, the suggested architecture does apply to some column- or row-bypassing multiplier. The throughput of those programs is dependent on multipliers, and when the multipliers are extremely slow, the performance of entire circuits will disappear

DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE LOW POWER EFFICIENT MULTIPLIER TO OVERCOME NBTI & PBTI EFFECTS

An identical phenomenon, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both effects degrade transistor speed, as well as in the lengthy term, the machine may fail because of timing violations. Digital multipliers are some of the most important arithmetic functional models. The general performance of those systems is dependent around the throughput from the multiplier. Meanwhile, the negative bias temperature instability effect happens whenever a pMOS transistor is under negative bias, growing the brink current from the pMOS transistor, and reducing multiplier speed. Therefore, you should design reliable high-performance multipliers. Within this paper, we advise a maturing-aware multiplier design having a novel adaptive hold logic circuit. The multiplier has the capacity to provide greater throughput with the variable latency and may adjust the AHL circuit to mitigate performance degradation that is a result of the maturing effect. Furthermore, the suggested architecture does apply to some column- or row-bypassing multiplier. The throughput of those programs is dependent on multipliers, and when the multipliers are extremely slow, the performance of entire circuits will disappear

DESIGN OF AGING –AWARE EFFICIENT BOOTH MULTIPLIER USING ADAPTIVE HOLD LOGIC

High speed and low consumption is one of the most important design objectives in integrated circuits. As multipliers are the most widely used components in such circuits, the multiplier must be designed efficiently. In this project the simple and efficient approach to reduce the maximum power consumption and delay, area in proposed. In this Existing system, negative bias temperature instability effect occurs when a Pmos transistor is under negative bias which increase the threshold voltage of the Pmos transistor and reduce the multiplier speed. Positive bias temperature in stability effect occers when an Nmos transistor is under positive bias .both effects degrade transistor and in long term the system may fail due to the timing violations. New technique implements serial multiplier architecture with booth algorithm .In proposed system, design of aging –aware efficient booth multiplier using adaptive hold logic circuit is introduced. The AHL circuit achieves reliable operation under the influence of NBTI and PBTI effects with this  proposed architecture 4x4 booth multiplier will developed and compare with contemporary architecture