Students’ acceptance towards kahoot application in mastering culinary terminology

Kahoot! is a game-based learning platform used to review students’ knowledge, for formative assessment and provides an opportunity not only to assess students' conceptual understanding but also to build new knowledge through further clarification during or after the game. The objective of this study is to assess the acceptability of culinary students in the use of Kahoot! application for mastery the culinary terminology. This study aimed to identify students' acceptance of learning applications, to identify students' acceptance of Kahoot! use in terms of memory as well as students' level of mastering Kahoot! in the learning process. This study is a descriptive study that used a five-point Likert scale questionnaire as an instrument. A total of 48 second year students from the Catering program were used as the study sample. The collected data were analyzed using Statistical Package for Social Science Version 23.0 for Windows (SPSS). The results show that the aspect of students' level of mastering the culinary terminology using Kahoot! application is high with a mean score of 4.55. Whereas the students’ acceptance of Kahoot! as a learning application, was also high with a mean score of 4.44. Finally, the students’ acceptance of the culinary terminology tested using Kahoot! is high with a mean score of 4.45

Beyond Moore's technologies: operation principles of a superconductor alternative

The predictions of Moore's law are considered by experts to be valid until 2020 giving rise to "post-Moore's" technologies afterwards. Energy efficiency is one of the major challenges in high-performance computing that should be answered. Superconductor digital technology is a promising post-Moore's alternative for the development of supercomputers. In this paper, we consider operation principles of an energy-efficient superconductor logic and memory circuits with a short retrospective review of their evolution. We analyze their shortcomings in respect to computer circuits design. Possible ways of further research are outlined.Comment: OPEN ACCES

Design of Adiabatic MTJ-CMOS Hybrid Circuits

Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic-in-memory structures in conjunction with CMOS. In this paper, we introduce a novel adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits. The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower power consumtion compared to the previous MTJ/CMOS full adder

VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design

In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4-phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as a design example that demonstrates the practicality of the proposed approach

Adiabatic elimination-based coupling control in densely packed subwavelength waveguides.

The ability to control light propagation in photonic integrated circuits is at the foundation of modern light-based communication. However, the inherent crosstalk in densely packed waveguides and the lack of robust control of the coupling are a major roadblock toward ultra-high density photonic integrated circuits. As a result, the diffraction limit is often considered as the lower bound for ultra-dense silicon photonics circuits. Here we experimentally demonstrate an active control of the coupling between two closely packed waveguides via the interaction with a decoupled waveguide. This control scheme is analogous to the adiabatic elimination, a well-known procedure in atomic physics. This approach offers an attractive solution for ultra-dense integrated nanophotonics for light-based communications and integrated quantum computing