A handheld high-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays

We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: 14 x 6 x 11 cm³, weight: 1.4 kg), the system is capable to detect<100 pM of Enterococcus faecalis derived DNA from a 2.5 μL sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in 0.18 μm CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT → 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption (120x), hardware volume (175x), and weight (96x)

A 64-channel, 1.1-pA-accurate on-chip potentiostat for parallel electrochemical monitoring

Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility

CMOS Architectures and circuits for high-speed decision-making from image flows

We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by exploiting bio-inspiration and performing processing tasks in parallel manner and concurrently with image acquisition. A vision system is presented which makes decisions within sub-msec range. This is very well suited for defense and security applications requiring segmentation and tracking of rapidly moving objects

A 16 x 16 CMOS amperometric microelectrode array for simultaneous electrochemical measurements

There is a requirement for an electrochemical sensor technology capable of making multivariate measurements in environmental, healthcare, and manufacturing applications. Here, we present a new device that is highly parallelized with an excellent bandwidth. For the first time, electrochemical cross-talk for a chip-based sensor is defined and characterized. The new CMOS electrochemical sensor chip is capable of simultaneously taking multiple, independent electroanalytical measurements. The chip is structured as an electrochemical cell microarray, comprised of a microelectrode array connected to embedded self-contained potentiostats. Speed and sensitivity are essential in dynamic variable electrochemical systems. Owing to the parallel function of the system, rapid data collection is possible while maintaining an appropriately low-scan rate. By performing multiple, simultaneous cyclic voltammetry scans in each of the electrochemical cells on the chip surface, we are able to show (with a cell-to-cell pitch of 456 μm) that the signal cross-talk is only 12% between nearest neighbors in a ferrocene rich solution. The system opens up the possibility to use multiple independently controlled electrochemical sensors on a single chip for applications in DNA sensing, medical diagnostics, environmental sensing, the food industry, neuronal sensing, and drug discovery

CMOS Vision Sensors: Embedding Computer Vision at Imaging Front-Ends

CMOS Image Sensors (CIS) are key for imaging technol-ogies. These chips are conceived for capturing opticalscenes focused on their surface, and for delivering elec-trical images, commonly in digital format. CISs may incor-porate intelligence; however, their smartness basicallyconcerns calibration, error correction and other similartasks. The term CVISs (CMOS VIsion Sensors) definesother class of sensor front-ends which are aimed at per-forming vision tasks right at the focal plane. They havebeen running under names such as computational imagesensors, vision sensors and silicon retinas, among others. CVIS and CISs are similar regarding physical imple-mentation. However, while inputs of both CIS and CVISare images captured by photo-sensors placed at thefocal-plane, CVISs primary outputs may not be imagesbut either image features or even decisions based on thespatial-temporal analysis of the scenes. We may hencestate that CVISs are more “intelligent” than CISs as theyfocus on information instead of on raw data. Actually,CVIS architectures capable of extracting and interpretingthe information contained in images, and prompting reac-tion commands thereof, have been explored for years inacademia, and industrial applications are recently ramp-ing up.One of the challenges of CVISs architects is incorporat-ing computer vision concepts into the design flow. Theendeavor is ambitious because imaging and computervision communities are rather disjoint groups talking dif-ferent languages. The Cellular Nonlinear Network Univer-sal Machine (CNNUM) paradigm, proposed by Profs.Chua and Roska, defined an adequate framework forsuch conciliation as it is particularly well suited for hard-ware-software co-design [1]-[4]. This paper overviewsCVISs chips that were conceived and prototyped at IMSEVision Lab over the past twenty years. Some of them fitthe CNNUM paradigm while others are tangential to it. Allthem employ per-pixel mixed-signal processing circuitryto achieve sensor-processing concurrency in the quest offast operation with reduced energy budget.Junta de Andalucía TIC 2012-2338Ministerio de Economía y Competitividad TEC 2015-66878-C3-1-R y TEC 2015-66878-C3-3-

ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.LOCUST IST2001—38 097VISTA TIC2003—09 817 - C02—01Office of Naval Research N000 140 210 88