A New electronic image array: The Active pixel charge injection device

This is a Ph.D. thesis dissertation in which a new type of image sensor is investigated as possible successor to the charge coupled device (CCD) for scientific applications. As a result of the work described in this dissertation, the active pixel charge injection device (AP-CID) has been developed. This device retains most of the positive features of both the charge injection device (CJD) imager (random readout, non destructive readout, antiblooming, increased UV sensitivity, radiation tolerance, low power consumption, low manufacturing price) and the CCD imager (low noise, high dynamic range). The device lacks most of the drawbacks of the aforementioned devices. A functional array architecture was created. Based on this architecture several devices were fabricated. One of the arrays was fully measured, characterized and suggestions for improvement were formulated. Most of the characterizationalysis work described in this dissertation was centered on the following issues: temporal noise, linearity and FPN. The measured noise performance of the new device is excellent and comparable to the noise performance of the scientific CCD. The newly developed sensor is necessary for scientific imaging applications in space based operation. However due to its qualities, this device could be used in a much wider range of applications including commercial digital cameras, spectroscopy, biological, nuclear and other scientific applications

Investigation of charge coupled device correlation techniques

Analog Charge Transfer Devices (CTD's) offer unique advantages to signal processing systems, which often have large development costs, making it desirable to define those devices which can be developed for general system's use. Such devices are best identified and developed early to give system's designers some interchangeable subsystem blocks, not requiring additional individual development for each new signal processing system. The objective of this work is to describe a discrete analog signal processing device with a reasonably broad system use and to implement its design, fabrication, and testing

Technical guidance for the development of a solid state image sensor for human low vision image warping

This report surveys different technologies and approaches to realize sensors for image warping. The goal is to study the feasibility, technical aspects, and limitations of making an electronic camera with special geometries which implements certain transformations for image warping. This work was inspired by the research done by Dr. Juday at NASA Johnson Space Center on image warping. The study has looked into different solid-state technologies to fabricate image sensors. It is found that among the available technologies, CMOS is preferred over CCD technology. CMOS provides more flexibility to design different functions into the sensor, is more widely available, and is a lower cost solution. By using an architecture with row and column decoders one has the added flexibility of addressing the pixels at random, or read out only part of the image

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications

Designing star trackers to meet micro-satellite requirements

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 2006.Includes bibliographical references (p. 179-187).Star trackers provide numerous advantages over other attitude sensors because of their ability to provide full, three-axis orientation information with high accuracy and flexibility to operate independently from other navigation tools. However, current star trackers are optimized to maximize accuracy, at the exclusion of all else. Although this produces extremely capable systems, the excessive mass, power consumption, and cost that result are often contradictory to the requirements of smaller space vehicles. Thus, it is of interest to design smaller, lower cost, albeit reduced capability star trackers that can provide adequate attitude and rate determination to small, highly maneuverable, low-cost spacecraft. This thesis discusses the analysis used to select hardware and predict system performance, as well as the algorithms that have been employed to determine attitude information and rotation rates of the spacecraft. Finally, the performance of these algorithms using computer simulated images, nighttime photographs, and images captured directly by star tracker prototypes is presented.by Kara M. Huffman.S.M

CIRCUITS AND ARCHITECTURE FOR BIO-INSPIRED AI ACCELERATORS

Technological advances in microelectronics envisioned through Moore’s law have led to powerful processors that can handle complex and computationally intensive tasks. Nonetheless, these advancements through technology scaling have come at an unfavorable cost of significantly larger power consumption, which has posed challenges for data processing centers and computers at scale. Moreover, with the emergence of mobile computing platforms constrained by power and bandwidth for distributed computing, the necessity for more energy-efficient scalable local processing has become more significant. Unconventional Compute-in-Memory architectures such as the analog winner-takes-all associative-memory and the Charge-Injection Device processor have been proposed as alternatives. Unconventional charge-based computation has been employed for neural network accelerators in the past, where impressive energy efficiency per operation has been attained in 1-bit vector-vector multiplications, and in recent work, multi-bit vector-vector multiplications. In the latter, computation was carried out by counting quanta of charge at the thermal noise limit, using packets of about 1000 electrons. These systems are neither analog nor digital in the traditional sense but employ mixed-signal circuits to count the packets of charge and hence we call them Quasi-Digital. By amortizing the energy costs of the mixed-signal encoding/decoding over compute-vectors with many elements, high energy efficiencies can be achieved. In this dissertation, I present a design framework for AI accelerators using scalable compute-in-memory architectures. On the device level, two primitive elements are designed and characterized as target computational technologies: (i) a multilevel non-volatile cell and (ii) a pseudo Dynamic Random-Access Memory (pseudo-DRAM) bit-cell. At the level of circuit description, compute-in-memory crossbars and mixed-signal circuits were designed, allowing seamless connectivity to digital controllers. At the level of data representation, both binary and stochastic-unary coding are used to compute Vector-Vector Multiplications (VMMs) at the array level. Finally, on the architectural level, two AI accelerator for data-center processing and edge computing are discussed. Both designs are scalable multi-core Systems-on-Chip (SoCs), where vector-processor arrays are tiled on a 2-layer Network-on-Chip (NoC), enabling neighbor communication and flexible compute vs. memory trade-off. General purpose Arm/RISCV co-processors provide adequate bootstrapping and system-housekeeping and a high-speed interface fabric facilitates Input/Output to main memory

Automated longwall guidance and control systems, phase 2, part 2: RCS, FAS, and MCS

The prototype preliminary design of the face advancement system (FAS) consisting of the yaw alignment system (YAS) and the roll control system (RCS), and the master control station (MCS) is outlined

A novel readout method for focal plane array imaging in the presence of large dark current

This research was an investigation of a novel readout method for focal plane array (FPA) optical imaging, especially for very sensitive detectors with large dark current. The readout method is based on periodically blocking the optical input enabling the removal of the dark current integration from the output. The research demonstrated that it is feasible to modulate the optical input with the designed readout circuit and thus achieve longer signal integration time to enhance the signal-to-noise ratio. Study of a proposed circuit model showed that in theory the correlated readout method could increase the output voltage swing and reduce the noise level by attenuating low frequency noise, thereby effectively improving the FPA dynamic range. Circuits based on standard CMOS circuitry were designed, simulated by PSpice, fabricated using Orbit 2µm n-well technology, and tested with a PI-4000 system. In the circuit evaluation, the output noise due to the clock switching phenomena, the gate signal feedthrough and the charge relaxation, was considered to be the critical problem. The most promising design for minimizing this problem had a CMOS current steering circuit at the input of a high CMRR operational amplifier. Simulation and test results showed that a modified capacitive transimpedance amplifier (CTIA) could subtract dark current output and reduce the output signal due to any difference between the frequencies of the optical input modulation signal and the switch modulation signal. In conclusion, the correlated readout circuit was shown to be a promising approach for advancing FPA technology