A high value, linear and tunable CMOS pseudo resistor for bio-medical applications

A sub-threshold MOS based pseudo resistor featuring a very high value and ultra-low distortion is proposed. A band-pass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The stand-alone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a lowpass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

A Fully Integrated Bio-potential Low-noise Amplifier Utilizing Capacitor Multipliers

In any biomedical signal acquisition system, a front-end amplifier is needed to amplify low amplitude bio-signals while filtering out any unwanted low-frequency artifacts. The design of low frequency poles within the sub-Hz range implies very large time-constants which goes against system integrability. In recent years, the pseudo resistor has been used to provide very large on-chip resistance to achieve sub-Hz pole frequency. However, the pseudo resistor behaves poorly across PVT variations and is highly non-linear which makes the low-frequency pole unpredictable. In this thesis, a bio-LNA utilizing a differential difference amplifier structure along with gm-C filters is examined. The differential topology provides high CMRR while the negative feedback through the gm-C filter provides the low-frequency pole. A capacitor multiplier is also implemented to achieve a very high value effective on-chip capacitance. The functionality of the bio-LNA is validated through simulations in Cadence

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Analog Compressive Sensing for Multi-Channel Neural Recording: Modeling and Circuit Level Implementation

RÉSUMÉ Dans cette thèse, nous présentons la conception d’un implant d’enregistrement neuronal multicanaux avec un échantillonnage compressé mis en oeuvre avec un procédé de fabrication CMOS à 65 nm. La réduction de la technologie a˙ecte à la baisse les paramètres des amplificateurs neuronaux couplés en AC, comme la fréquence de coupure basse, en raison de l’e˙et de canal court des transistors MOS. Nous analysons la fréquence de coupure basse et nous constatons que l’origine de ce problème, dans les technologies avancées, est la diminution de l’impédance d’entrée de l’amplificateur opérationnel de transconductance (OTA) en raison de la fuite d’oxyde de grille à l’entrée des OTA. Nous proposons deux solutions pour réduire la fréquence de coupure basse sans augmenter la valeur des condensateurs de rétroaction de l’étage d’entrée. La première solution est appelée rétroaction positive croisée et la deuxième solution utilise des PMOS à oxyde épais dans la paire de l’entrée di˙érentielle de l’OTA. Il est à noter que pour compresser le signal neuronal, nous utilisons le CS dans le domaine analogique. Pour la réalisation, un intégrateur à capacité commutée est requis. Les paramètres non idéaux de l’OTA utilisé dans cet intégrateur, tels que le gain fini, la bande passante, la vitesse de balayage et le changement rapide de la sortie. Toutes ces imperfections induisent des erreurs et réduisent le rapport signal sur bruit (SNR) total. Nous avons simulé ces imperfections sur Matlab et Simulink pour définir les spécifications de l’OTA requis. Aussi, pour concevoir les circuits analogiques correspondant aux interfaces neuronales requises, tels qu’un amplificateur neuronal, une référence de tension compacte et à faible consommation d’énergie est requise. Nous avons proposé une référence de tension de faible consommation d’énergie sans utiliser le transistor bipolaire parasite de la technologie CMOS pour diminuer la surface de silicium requise. Finalement, nous avons complété l’encodeur de CS et un convertisseur analogique-numérique à approximation successive (SAR ADC) requis pour la chaine d’enregistrement des signaux neuronaux dans ce projet.----------ABSTRACT In this thesis we present the design of a multi-channel neural recording implant with analog compressive sensing (CS) in 65 nm process. Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cuto˙ frequency due to the short-channel e˙ects of MOS transistors. We analyze the low-cuto˙ frequency and find that the main reason of this problem in advanced technologies is decreasing the input resistance of the operational transconductance amplifier (OTA) due to the gate oxide static current leakage in the input of the OTA. In advanced technologies, the gate oxide is thin and some electrons can penetrate to the channel and cause DC current leakage. We proposed two solutions to reduce the low-cuto˙ frequency without increasing the value of the feedback capacitors of the front-end neural amplifier. The first solution is called cross-coupled positive feedback, and the second solution is utilizing thick-oxide PMOS transistors in the input di˙erential pair of the OTA. Compress the neural signal, we utilized the CS method in analog domain. For its implementation, a switched-capacitor integrator is required. Non-ideal specifications of OTA of CS integrator such as finite gain, bandwidth, slew rate and output swing induce error and reduce the total signal to noise ratio (SNR). We simulated these non-idealities in Matlab and Simulink and extracted the specification of the required OTA. Also, to design analog circuits such as neural amplifier a low power and compact voltage reference is required. We implemented a low-power band-gap reference without utilizing parasitic bipolar transis-tor to decrease the silicon area. At the end, we completed the CS encoder and successive approximation architecture analog-to-digital converter (SAR ADC)

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 92×92µm for the implemented digital-backend

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 9292m for the implemented digital-backend