CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.Universidad Autónoma de Tlaxcala CACyPI-UATx-2017Program to Strengthen Quality in Educational Institutions C/PFCE-2016-29MSU0013Y-07-23National Council for Science and Technology 237991 22284

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Chaotic Oscillator Based Random Number Generator

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2005Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2005Bu çalışmada, yüksek hızlı, sürekli zaman LC-kaotik osilatör tasarlanmış ve bu osilatörün çıkışları rasgele bit üretiminde kullanılmıştır. Hem Bipolar hem de MOS transistorlu osilatör versiyonları için devre deklemleri türetilmiştir. Bu denklemlerin nümerik denklem çözücü programlar yardımıyla çözülmesiyle kaotik osilasyonun sağlandığı görülmüştür. Devreler, Spectre spice simülatörü ve IHP SGB25VD 0.25µm SiGeC BiCMOS prosesi model parametreleri kullanılarak test edilmiştir. Rasgele sayı üretimi, osilatör çıkışlarının 2 farklı referansla karşılaştırılmasıyla elde edilmektedir. Oluşturulan bitlerin istatistiksel özelliklerini iyileştirmek amacıyla Von-Neumann algoritması tasarlanarak entegre edilmiştir. Üretilen çıkış bitleri periyodik olmadığından anlamlı bitlerin oluşma anlarını belirten bir saat işareti tanımlanmıştır. Rasgele sayı üretimi için gerekli olan alt bloklar yüksek hızlı çalışmaya uygun olacak şeklide Emetör Bağlamalı Lojik ve Akım Modlu Lojik aileleri kullanılarak tasarlanmıştır. Spectre simülatöründe gerçekleştirilen simülasyonlar, tasarlanan rasgele bit üretecinin yaklaşık 300Mbit/s hızında çıkış oluşturabildiğini göstermiştir. Çıkış işaretlerini cip dışına alabilmek amacıyla Akım Modlu Lojik çıkış sürecüleri tasarlanmıştır. Kaotik osilatör ve rasgele bit üreteci sistemi, IHP SGB25VD 0.25µm SiGeC BiCMOS prosesi ile gerçeklenmiş ve üretime gönderilmiştir. Çipin toplam güç harcaması 50mW mertebesindedir. Toplam kırmık alanı 1 mm x 0.5 mm’dir.In this study, a high speed continuous time LC-chaotic oscillator was designed and utilized as a random bit generator. Circuit equations were derived for both MOS transistor and BJT versions. These equations were solved by using numeric solvers, and chaotic oscillation was observed. Spectre circuit simulator was used as the simulator. Circuits were verified by using IHP’s SGB25VD 0.25µm SiGeC BiCMOS process. To generate successive ‘1’s and ‘0’s, two comparators with different references were used. A well-known Von-Neumann de-skewing algorithm was also implemented in order to improve statistical properties of the generated bit stream. The clock signal was constructed using the outputs of the comparators in order to define the bit generation events. The random bit generation sub-blocks were implemented as bipolar Emitter Coupled Logic (ECL) and Current Mode Logic (CML) gates. Spectre simulations showed that the average throughput of the designed random bit generator is approximately 300Mbit/s. The CML output drivers were designed to output the generated data and clock signals. The whole system, including the BJT chaotic oscillator and the random bit generation sub-blocks, were implemented in IHP’s SGB25VD 0.25µm SiGeC BiCMOS process. The chaotic oscillator and the random bit generator block consume approximately 50mW power under typical conditions. Total area of the chip is 1 mm x 0.5 mm.Yüksek LisansM.Sc

Design and implementation of a multi-modal sensor with on-chip security

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

Chaotic Oscillations in CMOS Integrated Circuits

Chaos is a purely mathematical term, describing a signal that is aperiodic and sensitive to initial conditions, but deterministic. Yet, engineers usually see it as an undesirable effect to be avoided in electronics. The first part of the dissertation deals with chaotic oscillation in complementary metal-oxide-semiconductor integrated circuits (CMOS ICs) as an effect behavior due to high power microwave or directed electromagnetic energy source. When the circuit is exposed to external electromagnetic sources, it has long been conjectured that spurious oscillation is generated in the circuits. In the first part of this work, we experimentally and numerically demonstrate that these spurious oscillations, or out-of-band oscillations are in fact chaotic oscillations. In the second part of the thesis, we exploit a CMOS chaotic oscillator in building a cryptographic source, a random number generator. We first demonstrate the presence of chaotic oscillation in standard CMOS circuits. At radio frequencies, ordinary digital circuits can show unexpected nonlinear responses. We evaluate a CMOS inverter coupled with electrostatic discharging (ESD) protection circuits, designed with 0.5 μm CMOS technology, for their chaotic oscillations. As the circuit is driven by a direct radio frequency injection, it exhibits a chaotic dynamics, when the input frequency is higher than the typical maximum operating frequency of the CMOS inverter. We observe an aperiodic signal, a broadband spectrum, and various bifurcations in the experimental results. We analytically discuss the nonlinear physical effects in the given circuit : ESD diode rectification, DC bias shift due to a non-quasi static regime operation of the ESD PN-junction diode, and a nonlinear resonant feedback current path. In order to predict these chaotic dynamics, we use a transistor-based model, and compare the model's performance with the experimental results. In order to verify the presence of chaotic oscillations mathematically, we build on an ordinary differential equation model with the circuit-related nonlinearities. We then calculate the largest Lyapunov exponents to verify the chaotic dynamics. The importance of this work lies in investigating chaotic dynamics of standard CMOS ICs that has long been conjectured. In doing so, we experimentally and numerically give evidences for the presence of chaotic oscillations. We then report on a random number generator design, in which randomness derives from a Boolean chaotic oscillator, designed and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic oscillator is given by the Boolean delay equation. According to numerical analysis of the Boolean delay equation, a single node network generates chaotic oscillations when two delay inputs are incommensurate numbers and the transition time is fast. To test this hypothesis physically, a discrete Boolean chaotic oscillator is implemented. Using a CMOS 0.5 μm process, we design and fabricate a CMOS Boolean chaotic oscillator which consists of a core chaotic oscillator and a source follower buffer. Chaotic dynamics are verified using time and frequency domain analysis, and the largest Lyapunov exponents are calculated. The measured bit sequences do make a suitable randomness source, as determined via National Institute of Standards and Technology (NIST) standard statistical tests version 2.1

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

A Study on the Performance Enhancement of the Cascode FET Mixer Using New Common-Source and -Drain Configuration

The wireless communication system has become highly developed of late due to the emergence of various communication technologies, and it is becoming more widely used due to the various information requirements of its users. It has the advantages of mobility and accessibility due to easy information acquisition anytime and anywhere. Thus, the characteristics of low power consumption and high performance are required for the effective power management of the wireless communication system. It depends on a battery for system operation, however, whose efficiency and capacity for highly effective power management is still being investigated. Therefore, as the wireless communication system has limited power, it certainly requires effective RF circuits with low power consumption. The goal of this study is to develop a wireless communication system circuit with enhanced RF performance: the cascode FET mixer with new common-source and -drain circuit configuration. For the high performance of a wireless communication system with low power consumption, a well-designed RF circuit is certainly needed due to its large influence on the performance of the whole wireless communication system. If the mixer circuit is well designed, the whole wireless communication system will exhibit high performance. In this thesis, the enhanced-performance cascode FET mixer using new common-source and -drain circuit configuration is proposed. When the cascode FET mixer using new configuration was compared with the conventional one, it was found that the former has the performance of higher conversion gain at a lower input LO power, a very low noise figure, and very high LO-to-IF isolation. Thus, the proposed cascode FET mixer with enhanced RF performance can improve the performance of the wireless communication system, which can realize effective power consumption because of the use of a local oscillator with lower output power. The cascode FET mixer using new configuration was designed in this study based on the results of the simulation and measurement for the verification of the enhanced RF performance. The results showed the mixer’s enhanced RF performance compared with the conventional cascode FET mixer. The proposed new common-source and -drain circuit configuration in the cascode FET mixer is reported in this thesis for the first time. The cascode FET mixer using new configuration showed effective operation by means of the use of a local oscillator with lower output LO power. It also showed higher conversion gain with only the lower input LO power, which does not need a local oscillator with a large output power as it can be operated at lower input LO power compared with the conventional one. This is the important characteristic for the wireless communication system, which requires effective power consumption. The cascode FET mixer using new configuration showed very high LO-to-IF isolation without a LO rejection filter compared with the conventional one. It showed good LO-to-RF isolation. The cascode FET mixer using new configuration also showed a very low noise figure compared with the conventional one. It uses only a FET, which produces the effect to have very low noise figure due to the thermal and shot noise by an active device. The cascode FET mixer using new configuration showed low output IF power and low linearity for the output IF power of the fundamental and third-order intermodulation frequencies, low than those of the conventional one. It also showed the low output IF power spectrum for the intermodulation distortion of the low-side and up-side bands, as opposed to the conventional one. It showed that each reflection coefficients were about -30 dB for the RF frequency of 2.6 GHz, the LO frequency of 2.5 GHz, and the IF frequency of 100 MHz. Through the aforementioned study results, it is exhibited in this thesis that the proposed cascode FET mixer has enhanced RF performance by means of the new common-source and -drain circuit configuration. It can thus achieve high RF performance without an addition to any other circuit, for the enhancement of the RF performance. Especially, the cascode FET mixer using new configuration showed an indispensable circuit, which it must have to improve the efficiency of the wireless communication system due to the mobility and limited power.Chapter 1. Introduction 1 1.1 Background 2 1.2 Method of study 6 Chapter 2. Fundamental Concepts and Definition of Mixer 7 2.1 Definition of linearity and nonlinearity 8 2.2 Definition of frequency generation 13 2.3 Nonlinear phenomena 19 2.4 Definiton of power and gain 24 2.5 Stability 30 2.6 Mixer performance concept 32 Chapter 3. Cascode FET Mixer Design 46 3.1 Nonlinear FET devices 47 3.2 Conventional cascode FET mixer 57 3.3 Cascode FET mixer using new configuration 64 Chapter 4. Simulation and Measurement Results 76 4.1 Comparison of the simulation results 77 4.2 Comparison of the measurement results 95 Chapter 5. Conclusion 103 References 10

Organic electrochemical networks for biocompatible and implantable machine learning: Organic bioelectronic beyond sensing

How can the brain be such a good computer? Part of the answer lies in the astonishing number of neurons and synapses that process electrical impulses in parallel. Part of it must be found in the ability of the nervous system to evolve in response to external stimuli and grow, sharpen, and depress synaptic connections. However, we are far from understanding even the basic mechanisms that allow us to think, be aware, recognize patterns, and imagine. The brain can do all this while consuming only around 20 Watts, out-competing any human-made processor in terms of energy-efficiency. This question is of particular interest in a historical era and technological stage where phrases like machine learning and artificial intelligence are more and more widespread, thanks to recent advances produced in the field of computer science. However, brain-inspired computation is today still relying on algorithms that run on traditional silicon-made, digital processors. Instead, the making of brain-like hardware, where the substrate itself can be used for computation and it can dynamically update its electrical pathways, is still challenging. In this work, I tried to employ organic semiconductors that work in electrolytic solutions, called organic mixed ionic-electronic conductors (OMIECs) to build hardware capable of computation. Moreover, by exploiting an electropolymerization technique, I could form conducting connections in response to electrical spikes, in analogy to how synapses evolve when the neuron fires. After demonstrating artificial synapses as a potential building block for neuromorphic chips, I shifted my attention to the implementation of such synapses in fully operational networks. In doing so, I borrowed the mathematical framework of a machine learning approach known as reservoir computing, which allows computation with random (neural) networks. I capitalized my work on demonstrating the possibility of using such networks in-vivo for the recognition and classification of dangerous and healthy heartbeats. This is the first demonstration of machine learning carried out in a biological environment with a biocompatible substrate. The implications of this technology are straightforward: a constant monitoring of biological signals and fluids accompanied by an active recognition of the presence of malign patterns may lead to a timely, targeted and early diagnosis of potentially mortal conditions. Finally, in the attempt to simulate the random neural networks, I faced difficulties in the modeling of the devices with the state-of-the-art approach. Therefore, I tried to explore a new way to describe OMIECs and OMIECs-based devices, starting from thermodynamic axioms. The results of this model shine a light on the mechanism behind the operation of the organic electrochemical transistors, revealing the importance of the entropy of mixing and suggesting new pathways for device optimization for targeted applications