A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle

A study of Radiation-Tolerant Voltage-Controlled Oscillators designs in 65 nm bulk and 28 nm FDSOI CMOS technologies

Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices and communications systems that operate in radiation environments, where significant perturbations, especially in terms of phase noise, can be generated due to radiation particles. Among all the blocks that form a PLL system, previous research suggests the voltage-controlled oscillator (VCO) is one of the most critical components in terms of radiation tolerance and electric performance. Ring oscillators (ROs) and LC-tank VCOs have been commonly employed in high-performance PLLs. Nevertheless, both structures have drawbacks including a limited tuning range, high sensitivity to phase noise, limited radiation tolerance, and large design areas. In order to fulfill these high-performance requirements, a current-model logic (CML) based RO-VCO is presented as a possible solution capable of reducing the limitations of the commonly used structures and exploiting their advantages. The proposed hybrid VCO model includes passive components in its design which are the key parameters that define oscillation frequency of this structure. This tunable oscillator has been designed and tested in 65nm Bulk and 28 nm Fully depleted silicon-on-insulator (FDSOI) CMOS technologies The 65nm testchip was designed to compare the behavior of the proposed CML VCO with a current-starved RO and a radiation hardened by design (RHBD) LC-tank VCO in terms of tuning range, phase noise, Single event effect (SEE) sensitivity and design area. Simulations were carried out by applying a double exponential current pulse into different sensitive nodes of the three VCOs. In addition, SEE tests were conducted using pulsed laser experiments. Simulation and test results show that a CML VCO can effectively overcome the limitations presented by a RO-VCO and LC-tank VCO, achieving a wide range of tuning, and low sensitivity to noise and SEEs without the need for a large cross-section. Further studies of the proposed CML VCO were done on 28nm FDSOI in order to reduce the leakage current and increase the switching speed. the same current-starved VCO and CML VCO were implemented on this testchip, and simulations were performed by injecting a double exponential current pulse energy into the previously defined sensitive nodes. The results show SEE sensitivity improvement without narrowing the tuning range or affecting the phase noise response

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background- calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time DT of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output ◦range [0.42 - 2.52] V, over the temperature range [-20 , 85] C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems

Key issues and solutions for characterizing hot carrier aging of nano-meter scale nMOSFETs

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within a device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nano-devices, there are a number of challenges for characterizing their HCA: the random charge-discharge of traps in gate dielectric causes ‘within-a-device-fluctuation (WDF)’, making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nano-devices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation, σ, and mean value, µ. Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is little information on the accuracy of the extracted σ and µ. We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of 10 traps per device, the extracted µ and σ has an accuracy of ±14% and ±24% respectively with a 95% confidence

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Design and Simulation of Low Power Low Voltage Rail to Rail Operational Amplifier and the bandgap reference

运算放大器是模拟和混合电路中被广泛应用的基本模块，其精度和稳定性决定着系统的性能，而CMOS轨对轨运算放大器以其优异的输入、输出电压范围等特点受到广泛的应用。本文主要针对CMOS轨对轨运算放大器及其辅助电路带隙基准源进行设计与仿真。 本论文首先针对国内外低压低功耗轨对轨运算放大器做了广泛的调查和研究，在吸收前人成果的基础上，设计了一个低压低功耗轨对轨运算放大器。运算放大器采用两级运放的结构。运放的第一级采用互补差分对结构以实现轨对轨输入，采用折叠式共源共栅结构实现第一级的高增益。采用3倍电流镜技术来实现输入级的跨导的恒定。输出级采用浮动电流源控制的互补甲乙类输出结构，提高了输出电压的范围和效...Operational amplifiers are analog and mixed circuits are widely used in the basic module, its precision and stability determine the performance of the system, and rail to rail CMOS operational amplifier with excellent input and output voltage range and so on are widely used. This article will focus CMOS rail to rail operational amplifier and the auxiliary bandgap reference circuit design and simul...学位：工学硕士院系专业：物理与机电工程学院物理学系_微电子学与固体电子学学号：1982007115232