Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in CMOS process technology. The results analysis shows that the proposed CSLA structure takes only 30.385 ns which is better than the regular SQRT CSLA

Designing and Performance Evaluation of Carry Select Adder

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better than the conventional CSA and CSA with BEC

Implementation of Fast, Low Power and Area Efficient Carry Select Adder

One of the fastest adders is Carry Select Adder (CSLA) and it perform fast arithmetic functions in many data processing processors. A conventional CSLA has less carry propagation delay (CPD) than ripple carry adder (RCA). A compromise between RCA and carry look ahead adder is provided by Carry select adder. For the CSLA new logic is proposed by reducing redundant logic operations present in conventional CSLA. In the proposed scheme, schedule the carry select (CS) operation before final sum calculation. which is different approach from the conventional. Two carry words ( cin = 0 and 1) bit patterns and fixed cin bits use for generation units and CS logic optimization. Optimized logic units is used to obtain an efficient CSLA design. The proposed work is carried out using Modelsim SE 6.3f and Quatus2 software. DOI: 10.17762/ijritcc2321-8169.16046

Design of Low Power and Area Efficient Carry Select Adder (CSLA) using Verilog Language

Carry select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However conventional carry select adder (CSLA) is still area consuming due to the dual ripple carry adder structure. The excessive area overhead makes conventional carry select adder (CSLA) relatively unattractive but this has been the circumvented by the use of add-one circuit. In this an area efficient modified CSLA scheme based on a new first zero detection logic is proposed. The gate count in 32-bit modified CSLA can be greatly reduced, design proposed in this paper has been developed using VERILOG language and synthesized in XILINX13.2 version

EFFICIENT USAGE OF D LATCH FOR IMPLEMENTING A RELIABLE LOW POWER AREA CARRY SELECT ADDER

The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA

LOW COMPLEXITY D LATCH BASED CSLA FOR SPEED CRITICAL APPLICATIONS

The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA

Design of Static Segment Adder for Approximating Computing Applications

The digital VLSI design needs to attain high performance with desired reliability range. The high performance involves low power, area efficiency and high speed. This paper proposes a design of High speed energy efficient static segment adder (SSA) to enhance the overall performance based on approximation technique. Static segmentation includes both accurate and inaccurate part. The normal full adder performs accurate part and the carry select adder is used for inaccurate part. By using static segmentation the approximate computation is done. Approximate computing is a computation which generates “good enough” result rather than totally accurate result. Image processing is accomplished using SSA design. In this process 99.4% whole computational accuracy for 16 bit addition and also for 8 bit addition can be achieved

16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies

High speed, low power, and area efficient adders and comparators continue to play a key role in hardware implementation of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This thesis demonstrates a unique custom designed 16-bit adder in 250-nm CMOS technology to obtain fast and power/area efficient features by combining CPL and CS logic. Comparing the results obtained for proposed 16-bit Linear CPL/CS adder with the BEC (Binary Excess-1 Code) based low power SQRT-CS adder, the delay is reduced by approximately one thirds, power is reduced by 19.2%, and the number of transistors is reduced by 23.4%. Also, new tree-based 64-bit static and dynamic digital comparators are presented in this thesis to perform high speed and low power operations. This tree-based architecture combines a new approach of designing dynamic comparator using a low duty cycle clock to reduce the short circuit power consumption in pre-charge (or pre-discharge) mode. This work also introduces a new sizing strategy and load balancing techniques to improve self-pipelining tendency of a tree based design. A resource sharing technique is also integrated in both static and dynamic comparator designs. At 1.2V power supply in CMOS 90nm technology, worst path delay and worst power are 374ps and 822µW, respectively for low cost static design with 1244 (768+476) transistors in total. 768 transistors are used for resource sharing. The proposed full and partially dynamic designs show superior power efficiency compared to recent state of art designs. The worst power consumptions at 5GHz and 25% (50ps) duty cycle clock for the 64-bit full and partially dynamic comparator designs are 5.00mW and 2.78mW, respectively. 769 (320+449) transistors includes 320 transistors for resource sharing, and 1217 (768+449) includes 768 transistors for resource sharing for full and partial dynamic comparators, respectively

Modified Level Restorers Using Current Sink and Current Source Inverter Structures for BBL-PT Full Adder

Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process