442 research outputs found
Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability
The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced control of the performance and energy efficiency. Datapath control logic with NULL Cycle Reduction (NCR) and arbitration network are incorporated in the heterogeneous platform for large scale cascading. The platforms have been integrated with the data processing units using the IBM 130 nm 8RF process and fabricated using the MITLL 90 nm FDSOI process. Simulation and physical testing results show the energy efficiency advantage of asynchronous designs and the effective of the adaptive DVS mechanism in balancing the energy and performance in both platforms
An Architecture for High-throughput and Improved-quality Stereo Vision Processor
This paper presents the VLSI architecture to achieve high-throughput and
improved-quality stereo vision for real applications. The stereo vision processor
generates gray-scale output images with depth information from input images taken by
two CMOS Image Sensors (CIS). The depth estimator using the sum of absolute
differences (SAD) algorithm as stereo matching technique is implemented on hardware
by exploiting pipelining and parallelism. To produce depth maps with improved-quality
at real-time, pre- and post-processing units are adopted, and to enhance the adaptability
of the system to real environments, special function registers (SFRs) are assigned to
vision parameters. The design using 0.18um standard CMOS technology can operate at
120MHz clock, achieving over 140 frames/sec depth maps with 320 by 240 image size
and 64 disparity levels. Experimental results based on images taken in real world and
the Middlebury data set will be presented. Comparison data with existing hardware
systems and hardware specifications of the proposed processor will be given
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