3,488 research outputs found

    The impact of transistor aging on the reliability of level shifters in nano-scale CMOS technology

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    On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are

    High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

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    © Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

    A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

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    Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load

    Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter

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    In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new  low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with  our approach to the circuit. All the simulation results are based on 45nm CMOS technology and  simulated in cadence tool.DOI:http://dx.doi.org/10.11591/ijece.v3i5.316

    L-Band MMICs for Space-based SAR system

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    The design and performance of an L-Band GaAs chip-set is presented.The chip-set consists of a 6-bit attenuator circuit,a Low-Noise Amplifier (LNA)and a Multi Function Chip that is the combination of a 6-bit attenuator and 6-bit Phase shifter circuit.The chip-set is developed for the pre-flight engineering T/R (Transmit and Receive)modules currently in development with Astrium in a space-based SAR (Synthetic Aperture Radar)system.The MMICs are realised in the 0.25 µm PHEMT (PH25)technology of UMS.Only one iteration was needed for the MMICs in order to be fully compliant with the specifications

    Optimization study of high power static inverters and converters Final report

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    Optimization study and basic performance characteristics for conceptual designs for high power static inverter

    High voltage bias waveform generator for an RF MEMS microswitch

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    An integrated high voltage bias driver for a Radio Frequency Micro-Electro-Mechanical System (RF MEMS) microswitch is proposed. The design and implementation in a 0.7mum integrated circuit process with high and low voltage transistors is shown along with tested results. High voltage Double-Diffused Metal Oxide Semiconductor (DMOS) transistors in combination with low voltage digital logic provide a non-linear solution that achieves rise and fall times of 1mus while keeping power use to a minimum. System design and tradeoffs are presented for alternate approaches and combinations as well as future integration with Direct Current--Direct Current (DC-DC) voltage conversion and an internally generated clock

    Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

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    In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs).We propose a mixed TFET\u2013MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET\u2013MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET\u2013MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions

    유전알고리즘 및 강화학습을 사용한 고속 회로 설계 자동화 프레임워크

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    학위논문(석사) -- 서울대학교대학원 : 융합과학기술대학원 지능정보융합학과, 2022.2. 전동석.Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve 2.8-5.3× lower PDP than prior arts designed by human experts.설계 자동화는 대규모 디지털 시스템을 가능하게 하는 핵심 요소이지만 트랜지스터 수준에서 회로 설계 프로세스를 자동화하는 것은 여전히 어려운 과제로 남아 있습니다. 최근 연구에서는 아날로그 앰프와 같은 비교적 작은 회로에서 최적의 성능을 보이는 트랜지스터 크기를 찾기 위해 deep learning 알고리즘을 활용할 수 있다고 말합니다. 그러나 이러한 접근 방식은 주어진 설계 constraint를 충족하는 다른 회로 구조 탐색에 적용하기 어렵습니다. 본 연구에서는 성능과 신뢰성을 고려하여 각 트랜지스터의 크기를 최적화할 뿐만 아니라 처음부터 실용적인 회로 구조를 생성할 수 있는 자동 회로 설계 framework를 제안합니다. 우리는 framework를 사용하여 level shifter 회로를 설계했으며 실험 결과는 프레임워크가 새로운 level shifter 회로 토폴로지를 생성하고 자동으로 최적화된 설계가 인간 전문가가 설계한 선행 기술보다 2.8-5.3배 더 낮은 PDP를 달성한다는 것을 보여줍니다.Abstract i Contents ii List of Tables iv List of Figures v List of Algorithms vi 1 Introduction 1 2 Related work 6 2.1 Genetic Algorithm 6 2.2 NeuroEvolution of Augmenting Topologies (NEAT) 7 2.3 Reinforcement Learning (RL) 10 2.4 DDPG, D4PG, and PPO 12 2.5 Level Shifter 14 3 Proposed circuit design framework 17 3.1 Topology Generator 17 3.2 Circuit Optimizer 25 4 Experiment Result 32 4.1 Level Shifter Design 32 4.2 Topology Generation 34 4.3 Circuit Optimization 36 4.4 Test Chip Fabrication 42 4.5 Applicability of Topology Generator 47 5 Conclusion 50 Abstract (In Korean) 57석
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