38 research outputs found

    Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

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    This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed

    An Analog Phase Interpolation Based Fractional-N PLL

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    A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-conversion. This is achieved utilizing a feedforward mechanism for offset cancellation from the integer-N frequency. The design is implemented in a 0.13ฮผm CMOS process technology. A frequency resolution of 1.16Hz is achieved on a 5GHz differential delay cell VCO with a 100MHz reference oscillator. A ping-pong swallow counter topology alleviates pipeline latency to achieve 1-64 divide ratios. A digital pulse generator and nested phase-frequency detector provide tunable offset cancellation. A 5-bit current-steering DAC capable of 200ps pulses reduces output spurs. Theoretical calculations and Simulink modeling provides insight to the effects of non idealities in the system. Test structures and loop configurability are programmed via SPI interface through a custom GUI and prototype PCB

    ์ฐจ๋Ÿ‰์šฉ CIS Interface ๋ฅผ ์œ„ํ•œ All-Digital Phase-Locked Loop ์˜ ์„ค๊ณ„ ๋ฐ ๋ถ„์„

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    ํ•™์œ„๋…ผ๋ฌธ (์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ์ •๋•๊ท .This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์ž๋™์ฐจ CMOS ์ด๋ฏธ์ง€ ์„ผ์„œ (CIS) ์ธํ„ฐํŽ˜์ด์Šค๋ฅผ ์ง€์›ํ•˜ ๋Š” AD-PLL ์„ ์ œ์•ˆํ•œ๋‹ค. Automotive Physical ์‹œ์Šคํ…œ์˜ Gear 3 ๋ฅผ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•ด ์ œ์•ˆ๋œ AD-PLL ์€ 1.5 GHz ์—์„œ 3 GHz ์˜ ๋™์ž‘ ์ฃผํŒŒ์ˆ˜๋ฅผ ๊ฐ€์ง€๋ฉฐ, ๋‚ฎ ์€ RMS Jitter ๋ฐ PVT ๋ณ€ํ™”์— ๋Œ€ํ•œ ๋†’์€ ๋‘”๊ฐ์„ฑ์„ ๊ฐ–๋Š”๋‹ค. ์„ค๊ณ„์— ์•ž์„œ์„œ Matlab ๋ฐ Verilog Behavioral Simulation ์„ ํ†ตํ•ด Loop system ์˜ ์—ญํ•™์— ๋Œ€ํ•œ ์ž์„ธํ•œ ๋ถ„์„ ๋ฐ AD-PLL ์˜ Noise ๋ถ„์„์„ ์ˆ˜ํ–‰ํ•˜์˜€๊ณ , ์ด ๋ถ„์„์„ ๊ธฐ๋ฐ˜์œผ๋กœ ์ตœ์ ์˜ DLF gain ๊ณผ ์ •ํ™•ํ•œ ์ถœ๋ ฅ ์‘๋‹ต ๋ฐ ์„ฑ๋Šฅ์„ ์˜ˆ์ธก ํ•  ์ˆ˜ ์žˆ์—ˆ๋‹ค. ๋˜ํ•œ, ์ถœ๋ ฅ์˜ Phase Noise ์™€ RMS Jitter ๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•œ ์„ค๊ณ„ ๊ธฐ๋ฒ•์„ ์ž์„ธํžˆ ๋‹ค๋ฃจ๊ณ  ์žˆ์œผ๋ฉฐ ์ด๋ฅผ ์‹ค์ œ ๊ตฌํ˜„์— ํ™œ์šฉํ–ˆ๋‹ค. ์ œ์•ˆ๋œ ํšŒ๋กœ๋Š” 40 nm CMOS ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์œผ๋ฉฐ Decoupling Cap ์„ ์ œ์™ธํ•˜๊ณ  0.026 mm2 ์˜ ์œ ํšจ ๋ฉด์ ์„ ์ฐจ์ง€ํ•œ๋‹ค. ์ธก์ •๋œ ์ถœ๋ ฅ Clock ์‹ ํ˜ธ์˜ RMS Jitter ๊ฐ’์€ 2 GHz ์—์„œ 827 fs ์ด๋ฉฐ, ์ด 5.8 mW์˜ Power ๋ฅผ ์†Œ๋น„ํ•œ๋‹ค. ์ด ๋•Œ, ์ „์ฒด์ ์ธ ๊ณต๊ธ‰ ์ „์••์€ 0.9 V ์ด๋ฉฐ, Buffer ์˜ Power ๋งŒ์ด 1.1 V ๋ฅผ ์‚ฌ์šฉํ•˜ ์˜€๋‹ค.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 ์ดˆ ๋ก 72Maste

    Low phase noise, high bandwidth frequency synthesis techniques

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 243-249).A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be <100kHz for adequate phase noise performance to be achieved. Using the proposed technique, quantization noise is reduced to the point where intrinsic noise sources (VCO, charge-pump, reference and PFD noise) ultimately limit noise performance. An analytical model that draws an analogy between fractional-N frequency synthesizers and MASH A digital-to-analog converters is proposed. Calculated performance of a synthesizer implementing the proposed quantization noise reduction techniques shows excellent agreement with simulation results of a behavioral model. Behavioral modeling techniques that progressively incorporate non-ideal circuit behavior based on SPICE level simulations are proposed. The critical circuits used to build the proposed synthesizer are presented.(cont.) These include a divider retiming circuit that avoids meta-stability related to synchronizing an asynchronous signal, a timing mismatch compensation block used by a dual divider path PFD, and a unit element current source design for reduced output phase noise. Measurement results of a prototype 0.18/m CMOS synthesizer show that quantization noise is suppressed by 29dB when the proposed synthesizer architecture is compared to 2nd order EA frequency synthesizer. The 1MHz closed loop bandwidth allows the synthesizer to be modulated by up to 1Mb/s GMSK data for use as a transmitter with 1.8GHz and 900MHz outputs. The analytical model is used to back extract on-chip mismatch parameters that are not directly measurable. This represents a new analysis technique that is useful in the characterization of fractional-N frequency synthesizers.by Scott Edward Meninger.Ph.D

    Ultra Low-Power Frequency Synthesizers for Duty Cycled IoT radios

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    Internet of Things (IoT), which is one of the main talking points in the electronics industry today, consists of a number of highly miniaturized sensors and actuators which sense the physical environment around us and communicate that information to a central information hub for further processing. This agglomeration of miniaturized sensors helps the system to be deployed in previously impossible arenas such as healthcare (Body Area Networks - BAN), industrial automation, real-time monitoring environmental parameters and so on; thereby greatly improving the quality of life. Since the IoT devices are usually untethered, their energy sources are limited (typically battery powered or energy scavenging) and hence have to consume very low power. Today's IoT systems employ radios that use communication protocols like Bluetooth Smart; which means that they communicate at data rates of a few hundred kb/s to a few Mb/s while consuming around a few mW of power. Even though the power dissipation of these radios have been decreasing steadily over the years, they seem to have reached a lower limit in the recent times. Hence, there is a need to explore other avenues to further reduce this dissipation so as to further improve the energy autonomy of the IoT node. Duty cycling has emerged as a promising alternative in this sense since it involves radios transmitting very short bursts of data at high rates and being asleep the rest of the time. In addition, high data rates proffer the added advantage of reducing network congestion which has become a major problem in IoT owing to the increase in the number of sensor nodes as well as the volume of data they send. But, as the average power (energy) dissipated decreases due to duty cycling, the energy overhead associated with the start-up phase of the radio becomes comparable with the former. Therefore, in order to take full advantage of duty cycling, the radio should be capable of being turned ON/OFF almost instantaneously. Furthermore, the radio of the future should also be able to support easy frequency hopping to improve the system efficiency from an interference point of view. In other words, in addition to high data rate capability, the next generation radios must also be highly agile and have a low energy overhead. All these factors viz. data rate, agility and overhead are mainly dependent on the radio's frequency synthesizer and therefore emphasis needs to be laid on developing new synthesizer architectures which are also amenable to technology scaling. This thesis deals with the evolution of one such all-digital frequency synthesizer; with each step dealing with one of the aforementioned issues. In order to reduce the energy overhead of the synthesizer, FBAR resonators (which are a class of MEMS resonators) are used as the frequency reference instead of a traditional quartz crystal. The FBAR resonators aid the design of fast-startup oscillators as opposed to the long latency associated with the start-up of the crystal oscillator. In addition, the frequency stability of the FBAR lends itself to open-loop architecture which can support very high data rates. Another advantage of the open-loop architecture is the frequency agility which aids easy channel switching for multi-hop architectures, as demonstrated in this thesis

    Techniques for low jitter clock multiplication

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 115-121).Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.by Belal Moheedin Helal.Ph.D

    A SYSTEM-ON-CHIP 1.5 GHz PHASE LOCKED LOOP REALIZED USING 40 nm CMOS TECHNOLOGY

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    This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifierfeedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz

    Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

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    5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

    Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

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    Over the years Continuous-Time (CT) Sigma-Delta (ฮฃฮ”) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTฮฃฮ” modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. In other words, CTฮฃฮ” modulators are starting to offer the best of both worlds, with high resolution and high bandwidth. This dissertation focuses on the bandwidth and resolution of CTฮฃฮ” modulators. The goal of this research is to use the noise shaping benefits of CTฮฃฮ” modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. For this purpose, this research focuses on two different application areas that demand speed and resolution. These are a low-noise high-resolution time-to-digital converter (TDC), ideal for digital phase lock loops (PLL), and a very high-speed, wide-bandwidth CTฮฃฮ” modulator for wireless communication. The first part of this dissertation presents a new noise shaping time-to-digital converter, based on a CTฮฃฮ” modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, 30GHz and a 40GHz fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. Both prototypes are fabricated in a 65nm CMOS process. The standalone TDC achieves 81dB dynamic range and 13.2 equivalent number of bits (ENOB) with 176fs integrated-rms noise from 1MHz bandwidth. The in-band phase noise of the 30GHz digital fractional-N PLL is measured as -87dBc/Hz at a 100kHz offset which is equivalent to -212.6dBc/Hz2 normalized in-band phase noise. The second part of this dissertation focuses on high-speed (GS/s) CTฮฃฮ” modulators for wireless communication, and introduces a new time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTฮฃฮ” modulators. This new architecture shapes the digital-to-analog converter (DAC) mismatch effects in a CTฮฃฮ” modulator at GS/s operating speeds. It allows us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth. The prototype 5GS/s CTฮฃฮ” modulator with TI-RDWA is fabricated in 40nm CMOS and it achieves 156MHz bandwidth, 70dB dynamic range, 84dB SFDR and a Schreier FoM of 158.3dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138763/1/bdayanik_1.pd
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