DESIGN OF LOW POWER PULSE TRIGGERED FLIP FLOP USING CONDITIONAL PULSE- ENHANCEMENT SCHEME

Volume 2 Issue 1 (January 2014

Design of Low Power and Area Efficient Carry Select Adder (CSLA) using Verilog Language

Carry select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However conventional carry select adder (CSLA) is still area consuming due to the dual ripple carry adder structure. The excessive area overhead makes conventional carry select adder (CSLA) relatively unattractive but this has been the circumvented by the use of add-one circuit. In this an area efficient modified CSLA scheme based on a new first zero detection logic is proposed. The gate count in 32-bit modified CSLA can be greatly reduced, design proposed in this paper has been developed using VERILOG language and synthesized in XILINX13.2 version

Design of Low Power Data Preserving Flip Flop Using MTCMOS Technique

In order to reduce overall power consumption, a well-known technique is to scale supply voltages. However, to maintain performance, device threshold voltages must scale as well, which will cause sub threshold leakage currents to increase exponentially. The sub threshold voltage has to affect the two parameters one is the delay and other one is the sub threshold leakage current. Smaller the threshold voltage smaller will be delay while larger will be the sub threshold current. Controlling sub threshold leakage has been explored significantly in the literature, especially in the context of reducing leakage currents in burst mode type circuits, where the system spends the majority of the time in an idle standby, or sleep, state where no computation is taking place. MTCMOS or multi-threshold CMOS has been proposed as a very effective technique for reducing leakage currents during the standby by state by utilizing high sleep devices to gate the power supplies of a low logic block. Although MTCMOS circuit techniques are effective for controlling leakage currents in combinational logic, a drawback is that it can cause internal nodes to float, and cannot be directly used in standard memory cells without corrupting stored data. As a result, several researchers have explored possible MTCMOS latch designs that can reduce leakage currents yet maintain state during the standby modes. In this work a data preserving flip flop with reduced leakage power is designed using MTCMOS technique in 90nm technology with the help of CADENCE tool. The simulation results have shown that the leakage power is reduced by 25.70% compared to CMOS flip flop

Design techniques for low-power systems

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low-power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system including error control, system decomposition, communication and MAC protocols, and low-power short range networks

A low-voltage CMOS multiplier for RF applications

This work is part of a project funded under the Fourth Italian-Maltese Financial Protocol.A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 /spl mu/m CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.peer-reviewe

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

Low Power system Design techniques for mobile computers

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, sys tem decomposition, communication and MAC protocols, and low power short range net works