An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

Architecture of Micro Energy Harvesting Using Hybrid Input of RF, Thermal and Vibration for Semi-Active RFID Tag

This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device.This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device

Integrated cmos rectifier for rf-powered wireless sensor network nodes

This article presents a review of the CMOS rectifier for radio frequency energy harvesting application. The on-chip rectifier converts the ambient low-power radio frequency signal coming to antenna to useable DC voltage that recharges energy to wireless sensor network (WSN) nodes and radiofrequency identification (RFID) tags, therefore the rectifier is the most important part of the radio frequency energy harvesting system. The impedance matching network maximizes power transfer from antenna to rectifier. The design and comparison between the simulation results of one- and multi-stage differential drive cross connected rectifier (DDCCR) at the operating frequencies of 2.44GHz, and 28GHz show the output voltage of the multi-stage rectifier doubles at each added stage and power conversion efficiency (PCE) of rectifier at 2.44GHz was higher than 28GHz. The (DDCCR) rectifier is the most efficient rectifier topology to date and is used widely for passive WSN nodes and RFID tags

Study on Analog Front End of Passive UHF RFID Transponder

In this paper, an overview of passive Ultra High Frequency (UHF) Radio Frequency Identification (RFID) is presented. This literature review emphasis on the analog front end part of the RFID transponder based on several published papers conducted by previous researchers. A passive UHF RFID transponder chip design was proposed using 0.18 μm standard CMOS process. It is estimated to have power of 1μW and high efficiency that greater than 32%. This design will work in the range of frequency between 900MHz to 960MHz

Design And Implementation Of An X-Band Passive Rfid Tag

This research presents a novel fully integrated energy harvester, matching network, matching network,matching network, matching network,matching network, matching network, matching network, multi-stage RF-DC rectifier, mode selector, RC oscillator, LC oscillator, and X-band power amplifier implemented in IBM 0.18-µm RF CMOS technology. We investigated different matching schemes, antennas, and rectifiers with focus on the interaction between building blocks. Currently the power amplifier gives the maximum output power of 5.23 dBm at 9.1GHz. The entire RFID tag circuit was designed to operate in low power consumption. Voltage sensor circuit which generates the enable signal was designed to operate in very low current. All the test blocks of the RFID tag were tested. The smaller size and the cost of the RFID tag are critical for widespread adoption of the technology. The cost of the RFID tag can be lowered by implementing an on-chip antenna. We were able to develop, fabricate, and implement a fully integrated RFID tag in a smaller size (3 mm X 1.5 mm) than the existing tags. With further modifications, this could be used as a commercial low cost RFID tag

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

Design of Energy Harvester Module with a Low RF Power Input for UHF RFID Tag

An UHF RFID system is required to be able to operate at long range coverage, typically at 1-4 m. As a result, the RF signal power received at RFID Tag is very low, typically at -10 dBm. Moreover, practically most of commercially used RFID Tag is passive, which means that it solely relies on the RF signal transmitted from the RFID reader as the power source. Therefore, it is mandatory and critical to design an efficient and low input power RFID Tag system. In this paper, an energy harvester module for UHF RFID Tag, which is able to work at low RF input signal power and generate a stable DC voltage output, is designed. The module is able to operate at a very low RF input power as low as -10 dBm or equal to 100 mVpeak of induced voltage. To obtain such performance, a modified and optimized rectifier-using a Dynamic Vth Cancellation technique, is designed. By using this technique, the rectifier is able to produce an efficient and a high output voltage. Additionally, bandgap reference and voltage regulator circuits are designed to be independent of power supply and temperature variation. As the result, a stable DC power supply output is able to be generated. All the circuits are designed on Silterra 130nm CMOS technology. This technology allows us to design the transistor to operate at a low threshold voltage of 0.1 V, which is very suitable for the application of low input power UHF RFID Tag system

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices