60 research outputs found
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Low-cost duplication for separable error detection in computer arithmetic
Low-cost arithmetic error detection will be necessary in the future to ensure correct and safe system operation. However, current error detection mechanisms for arithmetic either have high area and energy overheads or are complex and offer incomplete protection against errors. Full duplication is simple, strong, and separable, but often is prohibitively costly. Alternative techniques such as arithmetic error coding require lower hardware and energy overheads than full duplication, but they do so at the expense of high design effort and error coverage holes. The goal of this research is to mitigate the deficiencies of duplication and arithmetic error coding to form an error detection scheme that may be readily employed in future systems. The techniques described by this work use a general duplication technique that employs an alternate number system in the duplicate arithmetic unit. These novel dual modular redundancy organizations are referred to as low-cost duplication, and they provide compelling efficiency and coverage advantages over prior arithmetic error detection mechanisms.Electrical and Computer Engineerin
Design of Soft Error Robust High Speed 64-bit Logarithmic Adder
Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice. The sampling instances have been set at 110 ps apart. In contrast to the traditional time redundancy, which requires two clock cycles to generate a given output, the SRA generates an output in a single clock cycle. The sampled sum outputs are compared using a 64-bit XOR tree to detect any possible error. An energy efficient 4-input transmission gate based XOR logic is implemented to reduce the delay and the power in this case. The pseudo-static logic (PSL), which has the ability to recover from a particle induced transient, is used in the adder implementation. In comparison with the space redundant approach which requires hardware duplication for error detection, the SRA is 50% more area efficient. The proposed SRA is simulated for different operands with errors inserted at different nodes at the inputs, the carry merge tree, and the sum generation circuit. The simulation vectors are carefully chosen such that the SET is not masked by error masking mechanisms, which are inherently present in combinational circuits. Simulation results show that the proposed SRA is capable of detecting 77% of the errors. The undetected errors primarily result when the SET causes an even number of errors and when errors occur outside the sampling window
Investigations into the feasibility of an on-line test methodology
This thesis aims to understand how information coding and the protocol that it
supports can affect the characteristics of electronic circuits. More specifically, it
investigates an on-line test methodology called IFIS (If it Fails It Stops) and its
impact on the design, implementation and subsequent characteristics of circuits
intended for application specific lC (ASIC) technology.
The first study investigates the influences of information coding and protocol on the
characteristics of IFIS systems. The second study investigates methods of circuit
design applicable to IFIS cells and identifies the· technique possessing the
characteristics most suitable for on-line testing. The third study investigates the
characteristics of a 'real-life' commercial UART re-engineered using the techniques
resulting from the previous two studies. The final study investigates the effects of the
halting properties endowed by the protocol on failure diagnosis within IFIS systems.
The outcome of this work is an identification and characterisation of the factors that
influence behaviour, implementation costs and the ability to test and diagnose IFIS
designs
Approximate logic circuits: Theory and applications
CMOS technology scaling, the process of shrinking transistor dimensions based
on Moore's law, has been the thrust behind increasingly powerful integrated circuits
for over half a century. As dimensions are scaled to few tens of nanometers, process
and environmental variations can significantly alter transistor characteristics, thus
degrading reliability and reducing performance gains in CMOS designs with technology
scaling. Although design solutions proposed in recent years to improve reliability
of CMOS designs are power-efficient, the performance penalty associated with these
solutions further reduces performance gains with technology scaling, and hence these
solutions are not well-suited for high-performance designs.
This thesis proposes approximate logic circuits as a new logic synthesis paradigm
for reliable, high-performance computing systems. Given a specification, an approximate
logic circuit is functionally equivalent to the given specification for a "significant"
portion of the input space, but has a smaller delay and power as compared to a
circuit implementation of the original specification. This contributions of this thesis
include (i) a general theory of approximation and efficient algorithms for automated
synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions
based on approximate circuits to improve reliability of designs with negligible
performance penalty, and (iii) efficient decomposition algorithms based on approxiiii
mate circuits to improve performance of designs during logic synthesis. This thesis
concludes with other potential applications of approximate circuits and identifies. open
problems in logic decomposition and approximate circuit synthesis
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A Performance-Efficient and Practical Processor Error Recovery Framework
Continued reduction in the size of a transistor has affected the reliability of pro-
cessors built using them. This is primarily due to factors such as inaccuracies while
manufacturing, as well as non-ideal operating conditions, causing transistors to slow
down consistently, eventually leading to permanent breakdown and erroneous operation
of the processor. Permanent transistor breakdown, or faults, can occur at any point in
time in the processor’s lifetime. Errors are the discrepancies in the output of faulty
circuits. This dissertation shows that the components containing faults can continue
operating if the errors caused by them are within certain bounds. Further, the lifetime
of a processor can be increased by adding supportive structures that start working
once the processor develops these hard errors.
This dissertation has three major contributions, namely REPAIR, FaultSim and
PreFix. REPAIR is a fault tolerant system with minimal changes to the processor
design. It uses an external Instruction Re-execution Unit (IRU) to perform operations,
which the faulty processor might have erroneously executed. Instructions that are
found to use faulty hardware are then re-executed on the IRU. REPAIR shows that
the performance overhead of such targeted re-execution is low for a limited number of
faults.
FaultSim is a fast fault-simulator capable of simulating large circuits at the transistor
level. It is developed in this dissertation to understand the effect of faults on different
circuits. It performs digital logic based simulations, trading off analogue accuracy with
speed, while still being able to support most fault models. A 32-bit addition takes
under 15 micro-seconds, while simulating more than 1500 transistors. It can also be
integrated into an architectural simulator, which added a performance overhead of 10 to 26 percent to a simulation. The results obtained show that single faults cause an
error in an adder in less than 10 percent of the inputs.
PreFix brings together the fault models created using FaultSim and the design
directions found using REPAIR. PreFix performs re-execution of instructions on a
remote core, which pick up instructions to execute using a global instruction buffer.
Error prediction and detection are used to reduce the number of re-executed instructions.
PreFix has an area overhead of 3.5 percent in the setup used, and the performance
overhead is within 5 percent of a fault-free case. This dissertation shows that faults
in processors can be tolerated without explicitly switching off any component, and
minimal redundancy is sufficient to achieve the same
The impact of soft errors in logic and its commercialisation in ARM IP
The significance of soft errors in logic has grown because of reduced memory
vulnerability and the shrinking dimensions of semiconductor technology coupled
with the increasing amount of logic integrated into a chip. Consequently, some
of ARM’s customers are concerned about how soft errors on the bus interconnect
will affect the dependability of their systems, since the interconnect is a critical
hub of communication in a SoC and represents a substantial and growing amount
of logic. With the rising complexity of their systems, the interconnect will
become larger and more complex in the future, adding to their concern. In this
work the impact of soft errors on the bus interconnect logic was investigated
and a product was developed to ameliorate the effects of such errors on ARM’s
customers’ products.
Methods to measure the SER of ARM IP were investigated by focusing on
logical masking, which is a component in the calculation of the SER. The effect
that the topology of a combinatorial logic circuit has on its logical masking rate
was considered by performing gate-level statistical fault injection on different
implementations of adder circuits. Significant variation in logical masking was
found ranging from a factor of 3.1 at a synthesis frequency of 100 MHz to a factor
of 2.1 at 900 MHz. This difference is explained in an original way by correlating
logical masking with the circuit’s path length and fan-out. These properties
could be used to create a static method of measuring the logical masking rather
than the current time-consuming method of dynamic simulation. Additionally,
nearly 30% of faults injected cause more than one error, which means that the
combinational SER will be underestimated if research does not take gate fan-out
into consideration. Using this methodology a circuit designer can now base his
choice or development of a circuit on its reliability as well as its performance,
power, and area. Studying the variation in the factors that affect the SER is
important to ensure accuracy in addressing customer requirements.
Although it is important to consider the rate of soft error occurrence, in this
work the impact of errors is demonstrated to be critical. Using protocol-level
fault injection it is shown that faults on the ARM AXI bus interconnect can have
a serious effect on the reliability of the entire SoC such as deadlock, memory
corruption, or undefined behaviour. Using a fault-path traversal algorithm,
it is demonstrated that traditional error detection codes are not sufficient at
preventing these failures when faults occur on certain AXI bus signals. This led
to the development of novel fault tolerant methods that provide protection for
these identified signals. Based on these developments, a product was proposed for
an add-on to the AXI bus interconnect that can detect, correct, and report logic
soft errors without changing the AMBA standard or the customer’s connecting
IP
The 1992 4th NASA SERC Symposium on VLSI Design
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design
Soft error analysis and mitigation in circuits involving C-elements
PhD ThesisA SEU or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption.
The first part of this thesis studies the impact of process variation, temperature, voltage and size scaling within the same process on the vulnerability of the nodes of C-element circuits. The objectives are to identify vulnerable to SEU nodes inside a C-element and to find the critical charge needed to flip the output from low to high (0-1) and high to low (1-0) on different implementations of C-elements.
In the second part, a framework to compute the SEU error rates is developed. The error rates of circuits are a trade-off between the size of the transistors and the total area of vulnerability. Comparisons of the vulnerability of different configurations of a C-element are made, and error rates are calculated.
The third part focuses on soft error mitigation for single and dual rail latches. The latches are able to detect and correct errors due to SEU. The functionalities of the solutions have been validated by simulation. A comprehensive analysis of the performance of the latches under variations of the process and temperature are presented.
The fourth part focuses on testing of the new latches. The objective is to design complex systems and incorporate both single rail and dual rail latches in the systems. Errors are injected in the latches and the functionality of the error correcting latches towards the SEU errors are observed at their outputs.
The framework to compute error rates and soft error mitigation developed in this thesis can be used by designers in predicting the occurrence of soft error and mitigating soft error in systems
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High integrity hardware-software codesign
Programmable logic devices (PLDs) are increasing in complexity and speed, and are being used as important components in safety-critical systems. Methods for developing high-integrity software for these systems are well-known, but this is not true for programmable logic. We propose a process for developing a system incorporating software and PLDs, suitable for safety critical systems of the highest levels of integrity. This process incorporates the use of Synchronous Receptive Process Theory as a semantic basis for specifying and proving properties of programs executing on PLDs, and extends the use of SPARK Ada from a programming language for safety-critical systems software to cover the interface between software and programmable logic. We have validated this approach through the specification and development of a substantial safety-critical system incorporating both software and programmable logic components, and the development of tools to support this work. This enables us to claim that the methods demonstrated are not only feasible but also scale up to realistic system sizes, allowing development of such safety-critical software-hardware systems to the levels required by current system safety standards
The 1991 3rd NASA Symposium on VLSI Design
Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2
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