4,022 research outputs found

    A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

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    Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow

    Real-Time Selective Harmonic Minimization for Multilevel Inverters Using Genetic Algorithm and Artificial Neural Network Angle Generation

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    This work approximates the selective harmonic elimination problem using Artificial Neural Networks (ANN) to generate the switching angles in an 11-level full bridge cascade inverter powered by five varying DC input sources. Each of the five full bridges of the cascade inverter was connected to a separate 195W solar panel. The angles were chosen such that the fundamental was kept constant and the low order harmonics were minimized or eliminated. A non-deterministic method is used to solve the system for the angles and to obtain the data set for the ANN training. The method also provides a set of acceptable solutions in the space where solutions do not exist by analytical methods. The trained ANN is a suitable tool that brings a small generalization effect on the angles\u27 precision and is able to perform in real time (50/60Hz time window)

    Contributions on spectral control for the asymmetrical full bridge multilevel inverter

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    Las topologías de circuitos inversores multinivel pueden trabajar a tensiones y potencias mayores que las alcanzadas por convertidores convencionales de dos niveles. Además, la conversión multinivel reduce la distorsión armónica de las variables de salida y en algunos casos, a pesar del aumento de elementos de conmutación, también reduce las pérdidas de conversión al incrementarse el número de niveles. La reducción de distorsión alcanzada por el número de niveles puede aprovecharse para reducir las pérdidas de conmutación disminuyendo la frecuencia de las señales portadoras. Para reducir aún más esta frecuencia sin degradar el espectro, nosotros controlamos las pendientes de las portadoras triangulares. Primero se han desarrollado dos modelos analíticos para predecir el espectro del voltage de salida, dependiendo de: el índice de modulación MA, la razón de distribución de voltaje K de las fuentes de alimentación , y las cuatro pendientes de las portadoras{r1, r2, r3, r4}. El primer modelo considera el Muestreo Natural y se basa en Series Dobles de Fourier (SDF) mientras que el segundo modelo, utiliza la Serie Sencilla de Fourier (SSF) introduciendo el concepto de Muestreo Pseudo-Natural, una aproximación digital de la modulación natural. Ambos modelos son programados en Matlab, verificados con Pspice y validados con un prototipo experimental que contiene un modulador digital implementado con DSP.La concordancia entre las modulaciones natural y pseudo-natural, asi como entre sus respectivos modelos, es aprovechada por un algorítmo genético (AG) donde la THD es la función costo a reducir. Después de varios ensayos y de sintonizar el AG, se genera una matriz que contiene conjuntos de portadoras optimizadas dentro un rango específico de las variables {MA,K} y es probada con un segundo prototipo en lazo cerrado. Un lazo lento digital modifica las portadoras creadas por un dsPIC en modulaciones PWM; estas son demoduladas y sus amplitudes corregidas por un lazo de acción anticipada. Estas portadoras se comparan con una referencia sinusoidal que a su vez es modificada por variables de estado, generando finalmente la modulación multinivel en lazo cerrado. Los resultados finales demuestran la fiabilidad de la reducción de armónicos usando la programación de las pendientes de las portadoras. Palabras claves: inversor multinivel, PWM, distorsión armónica, modelo espectral, pendiente de portadora, conjunto de portadoras, distribución de niveles, Serie Doble de Fourier, Serie Simple de Fourier, muestreo natural, muestreo regular, muestreo pseudo-natural , Algoritmos Genéticos.Multilevel inverter (MI) topologies can work at higher voltage and higher power than conventional two-level converters. In addition, multilevel conversion reduces the output variables harmonic distortion and, sometimes, in spite of the devices-count increment, the conversion losses can also decrease by increasing the number of levels. The harmonic distortion reduction achieved by increasing the number of levels, can be used to further reducing the switching losses by decreasing the inverter carrier frequencies. To reduce even more the switching frequency without degrading output spectrum, we control the triangular carrier waveforms slopes. First, to achieve this target, two analytical models have been created in order to predict the inverter output voltage spectrum, depending on diverse parameters: the amplitude modulation index MA, the voltage distribution K of the inverter input sources, and the four carrier slopes {r1, r2, r3, r4}. The first model considers Natural Sampling and is based on Double Fourier Series (DFS) whereas the second model based on Simple Fourier Series (SFS), introduces the concept of Pseudo-Natural Sampling, as a digital approximation of the natural modulation. Both models are programmed in Matlab, verified with Pspice simulations and validated with a first experimental prototype with a DSP digital modulator.The good agreement between natural and pseudo-natural modulations, as well as their respective DFS and SFS models, is exploited by a Genetic Algorithm (GA) application where THD is the cost function to minimize. After testing and properly tuning the GA, a framework matrix containing the optimized carriers set for a specific range of variables {MA,K} is generated and then, tested with a second, closed-loop prototype. A slow digital loop modifies the carrier slopes created by dsPIC microcontroller as PWM modulations, whose amplitude, once demodulated, are affected by a feed-forward loop. These carriers, compared with a sinusoidal reference, state-feedback modified, generate finally the closed-loop multilevel modulation. The final results demonstrates the feasibility of harmonic reduction by means of carrier slopes programming. Keywords: multilevel inverter, PWM, harmonic distortion, spectral modeling, carrier slope, carriers set, level distribution, Double Fourier Series, Simple Fourier Series, natural sampling, regular sampling, pseudo-natural sampling, Genetic Algorithms

    Compilation and Scheduling Techniques for Embedded Systems

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    Embedded applications are constantly increasing in size, which has resulted in increasing demand on designers of digital signal processors (DSPs) to meet the tight memory, size and cost constraints. With this trend, memory requirement reduction through code compaction and variable coalescing techniques are gaining more ground. Also, as the current trend in complex embedded systems of using multiprocessor system-on-chip (MPSoC) grows, problems like mapping, memory management and scheduling are gaining more attention. The first part of the dissertation deals with problems related to digital signal processors. Most modern DSPs provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. A careful placement of variables in memory is important in decreasing the number of address arithmetic instructions leading to compact and efficient code. Chapters 2 and 3 present effective heuristics for the simple and the general offset assignment problems with variable coalescing. A solution based on simulated annealing is also presented. Chapter 4 presents an optimal integer linear programming (ILP) solution to the offset assignment problem with variable coalescing and operand permutation. A new approach to the general offset assignment problem is introduced. Chapter 5 presents an optimal ILP formulation and a genetic algorithm solution to the address register allocation problem (ARA) with code transformation techniques. The ARA problem is used to generate compact codes for array-intensive embedded applications. In the second part of the dissertation, we study problems related to MPSoCs. MPSoCs provide the flexibility to meet the performance requirements of multimedia applications while respecting the tight embedded system constraints. MPSoC-based embedded systems often employ software-managed memories called scratch-pad memories (SPM). Scheduling the tasks of an application on the processors and partitioning the available SPM budget among those processors are two critical issues in reducing the overall computation time. Traditionally, the step of task scheduling is applied separately from the memory partitioning step. Such a decoupled approach may miss better quality schedules. Chapters 6 and 7 present effective heuristics that integrate task allocation and SPM partitioning to further reduce the execution time of embedded applications for single and multi-application scenarios

    Switched-battery boost-multilevel inverter with GA optimized SHEPWM for standalone application

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    This paper presents a boost-multilevel inverter design with integrated battery energy storage system for standalone application. The inverter consists of modular switched-battery cells and a full-bridge. It is multifunctional and has two modes of operation: the charging mode which charges the battery bank and the inverter mode which supplies AC power to the load. This inverter topology requires significantly less power switches compared to conventional topology such as cascaded H-bridge multilevel inverter, leading to reduced size/cost and improved reliability. To selectively eliminate low-order harmonics and control the desired fundamental component, nonlinear system equations are represented in fitness function through the manipulation of modulation index and the Genetic Algorithm is employed to find the optimum switching angles. A 7-level inverter prototype is implemented and experimental results are provided to verify the feasibility of the proposed inverter design

    Design of Outrunner Eectric Machines for Green Energy Applications

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    Interests in using rare-earth free motors such as switched reluctance motors (SRMs) for electric and hybrid electric vehicles (EV/HEVs) continue to gain popularity, owing to their low cost and robustness. Optimal design of an SRM, to meet specific characteristics for an application, should involve simultaneous optimization of the motor geometry and control in order to achieve the highest performance with the lowest cost. This dissertation firstly presents a constrained multi-objective optimization framework for design and control of a SRM based on a non-dominated sorting genetic algorithm II (NSGA-II). The proposed methodology optimizes SRM operation for high volume traction applications by considering multiple criteria including efficiency, average torque, and torque ripple. Several constraints are defined by the application considered, such as the motor stack length, minimum desired efficiency, etc. The outcome of this optimization includes an optimal geometry, outlining variables such as air gap length, rotor inner diameter, stator pole arc angle, etc as well as optimal turn-on and turn-off firing angles. Then the machine is manufactured according to the obtained optimal specifications. Finite element analysis (FEA) and experimental results are provided to validate the theoretical findings. A solution for exploring optimal firing angles of nonlinear current-controlled SRMs is proposed in order to minimize the torque ripple. Motor torque ripple for a certain electrical load requirement is minimized using a surrogate-based optimization of firing angles by adjusting the motor geometry, reference current, rotor speed and dc bus voltage. Surrogate-based optimization is facilitated via Neural Networks (NN) which are regression tools capable of learning complex multi-variate functions. Flux and torque of the nonlinear SRM is learned as a function of input parameters, and consequently the computation time of design, which is crucial in any micro controller unit, is expedited by replacing the look-up tables of flux and torque with the surrogate NN model. This dissertation then proposes a framework for the design and analysis of a coreless permanent magnet (PM) machine for a 100 kWh shaft-less high strength steel flywheel energy storage system (SHFES). The PM motor/generator is designed to meet the required specs in terms of torque-speed and power-speed characteristics given by the application. The design challenges of a motor/generator for this architecture include: the poor flux paths due to a large scale solid carbon steel rotor and zero-thermal convection of the airgap due to operation of the machine in vacuum. Magnetic flux in this architecture tends to be 3-D rather than constrained due to lack of core in the stator. In order to tackle these challenges, several other parameters such as a proper number of magnets and slots combination, number of turns in each coil, magnets with high saturated flux density and magnets size are carefully considered in the proposed design framework. Magnetic levitation allows the use of a coreless stator that is placed on a supporting structure. The proposed PM motor/generator comprehensive geometry, electromagnetic and mechanical dimensioning are followed by detailed 3-D FEA. The torque, power, and speed determined by the FEA electromagnetic analysis are met by the application design requirements and constraints for both the charging and discharging modes of operation. Finally, the motor/generator static thermal analysis is discussed in order to validate the proposed cooling system functionality

    Optimal excitation controllers, and location and sizing of energy storage for all-electric ship power system

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    The Navy\u27s future all-electric ship power system is based on the integrated power system (IPS) architecture consisting of power generation, propulsion systems, hydrodynamics, and DC zonal electric distribution system (DC-ZEDS). To improve the power quality, optimal excitation systems, and optimal location and sizing of energy storage modules (ESMs) are studied. In this dissertation, clonal selection algorithm (CSA) based controller design is firstly introduced. CSA based controller design shows better exploitation ability with relatively long search time when compared to a particle swarm optimization (PSO) based design. Furthermore, \u27optimal\u27 small population PSO (SPPSO) based excitation controller is introduced. Parameter sensitivity analysis shows that the parameters of SPPSO for regeneration can be fined tuned to achieve fast optimal controller design, and thus exploiting SPPSO features for problem of particles get trapped in local minima and long search time. Furthermore, artificial immune system based concepts are used to develop adaptive and coordinated excitation controllers for generators on ship IPS. The computational approaches for excitation controller designs have been implemented on digital signal processors interfaced to an actual laboratory synchronous machine, and to multimachine electric ship power systems simulated on a real-time digital simulator. Finally, an approach to evaluate ESM location and sizing is proposed using three metrics: quality of service, survivability and cost. Multiple objective particle swarm optimization (MOPSO) is used to optimize these metrics and provide Pareto fronts for optimal ESM location and sizing --Abstract, page iv
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