Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

A wireless biomedical telemetry system is a device that collects biomedical signal measurements and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedical devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable device. The focus of this work is on development of an electronic front-end for wireless powering of an implantable biomedical device. The energy harvesting front-end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front-end circuit is developed in 0.13um CMOS technology with careful attention to analog layout issues. Post-layout simulation results are presented for each sub-block as well as the full front-end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5uA The complete power receiver front-end has a power conversion efficiency of up to 29%

Analogue micropower FET techniques review

Accepted versio

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Regulated Cascode Current Mirror with Improved Voltage Swing

This paper presents a simple and easy-to-use method allowing to improve output swing of regulated cascode CMOS current mirror with short channel devices. It is based on matched offset voltage generators, implemented simultaneously at the input and output of the current mirror. These voltage generators translate the drain voltages of the reference and source transistors to the saturation voltage VDSAT, i.e. to minimal level, ensuring high output resistance of the cascode. The design aims to provide a nanosecond current generator for optical laser source, with fast short channel devices facilitating the integration. This paper presents a concept of circuit implementation, a mathematical description of the optimal value of voltage offset, and simulation results in 40nm process

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

Exploiting the bulk-driven approach in CMOS analogue amplifier design

This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused – at the input-stage of differential pairs, at the source followers, and at the cascode devices. For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the author’s best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented. The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of the OTA exceeds 60dB using a 0.35μm CMOS technology. The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.