47,760 research outputs found

    A low noise, sub-1ppm/oC piecewise second-order curvature compensated bandgap reference for high resolution ADC

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    학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.본 논문에서는 고해상도 analog to digital converter를 위한 저 잡음, 고 정밀 bandgap voltage reference를 제안한다. reference 회로의 성능 중 가장 중요한 것들은 바로 낮은 온도 계수(temperature coefficient)와 저주파 대역의 전기적 잡음이다. 제안된 Bandgap reference 회로는 위 두가지 요소를 개선 하였다. 먼저 낮은 온도 계수를 성취하기 위해서는 BJT Emitter-Base전압의 비선형적 온도의존성을 보상해주어야 하고, bandgap core을 이루는 Error amplifier의 DC offset을 제거해야 하며, 마지막으로 process variation에의한 추가적인 온도 의존성을 상쇄시켜야 한다. 제안된 bandgap reference는 여러가지 회로 기술들을 활용해 위 요소들을 보상하였다. BJT Emitter-Base전압의 비선형적 온도 의존성을 온도에 대해 2차 의존성을 갖는 compensation 전류를 생성하고 bandgap core에 흘려주어 제거하였다. Compensation 전류는 크게 current subtraction 동작과 current squaring 동작을 통해 생성되는데, 위 동작은 모두 process variation에 둔감하다. 두 번 째로 process variation에 의한 온도 특성의 변화를 보상해 주기 위해 trimming resistor를 사용하였다. 마지막으로 error amplifier에 chopping을 적용하여 Error amplifier DC offset을 약화시켰다. Bandgap reference의 저 주파수 전기적 잡음의 근원은 대부분 Error amplifier이므로 chopping 동작을 통해 저주파대역의 전기적 잡음 또한 제거된다. Chopping 동작을 통해 생겨난 리플 과, 고주파 대역으로 변조된 저주파 대역의 전기적 잡음은 RC filter를 통해 제거하였다. 제안된 bandgap reference는 스탠다드 0.13um CMOS 공정의 3.3V 전원 소자로 설계하였으며 레이아웃 사이즈는 0.0534mm2이다. Post layout simulation 결과 제안된 bandgap reference의 -40°C부터 125°C 사이의 온도 계수는 약 0.64ppm/°C이다. 0.1Hz부터 10Hz사이의 integrated noise는 약 2.7uVrms이다. 제안된 bandgap reference는 상온에서 약 44uA의 전류를 소모한다.In this thesis a low noise and high precision bandgap reference is presented. One of the most important characteristics of reference circuit for analog to digital converter with high resolution is low temperature drift and low noise. The proposed bandgap reference improves these two characteristics. To achieve low temperature coefficient(TC), non-linear temperature dependence of emitter-base voltage of bipolar transistor should be compensated. Also, degradation of TC due to dc offset of the error amplifier and process variation is another concern. The proposed bandgap reference compensates these factors by utilizing various circuit technique. Because non-linear temperature dependence of bipolar transistor has a concave shape with temperature, second order curvature compensation current is generated by using current subtraction circuit and current squaring circuit and injected into bandgap core. The current subtraction and squaring operation is tolerant to process variation. To achieve low temperature coefficient regardless of process variation, PTAT trimming is utilized to compensate added linear temperature dependence. At last, to remove dc offset of the error amplifier, chopping technique is applied to the error amplifier. Ripple and up-modulated low frequency caused by chopping operation is removed through RC-filter. The proposed bandgap reference is designed in 0.13um standard CMOS process. Layout size of the bandgap reference is 0.0534mm2. Post layout simulation shows that TC of the bandgap reference from -40°C to 125 °C is 0.64ppm/°C. In addition, integrated noise from 0.1Hz to 10Hz is about 2.7uVrms. The proposed bandgap reference consumes 44uA at room temperature제 1 장 서론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 bandgap reference의 동작 원리. 4 1. bipolar 트랜지스터의 온도 특성 4 2. 기본적인 bandgap voltage reference의 동작 원리 7 3. 기본적인 bandgap current reference의 동작 원리 9 제 2 장 기본적인 bandgap reference의 성능적 한계 12 제 1 절 비선형적 온도 의존성 12 1. error amplifier dc offset 14 2. emitter-base 전압의 비선형적 온도 의존성 16 3. bipolar 트랜지스터 전류 이득에 의한 비선형적 온도 의존성 17 4. bipolar 트랜지스터의 베이스 저항에 의한 비선형적 온도 의존성 19 제 2 절 Bandgap reference의 전기적 잡음. 20 제 3 장 제안하는 저 잡음 고 정밀 bandgap voltage reference 22 제 1절 제안된 bandgap reference의 전체 구조 22 1. PTAT전류 생성 회로 23 2. reference 전류 생성 회로 24 3. bandgap core 25 제 2절 Curvature compensation technique 25 제 3절 Noise reduction technique 30 제 4절 Resistor trimming 32 제 5절 주요 성분 파라 미터 테이블 33 제 4 장 Layout 및 모의 실험 결과 34 제 1 절 Layout 34 제 2 절 모의 실험 결과 35 제 5 장 결론 40 제 6 장 부록 current squaring 회로의 동작 원리. 41 참고문헌 43 Abstract 43Maste

    A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator

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    Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand

    An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

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    This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

    A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

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    An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

    Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

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    Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

    The operation of an ISFET as an electronic device

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    Bipolar Analog-to-pulse Width Converter

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    Bipolar analog-to-pulse width converter to implement analog-to-digital conversion in spacecraft system

    An Offset Cancelation Technique for Latch Type Sense Amplifiers

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    An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW
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