A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC

The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irradiation. Various gain selection algorithms to achieve the extended dynamic range are implemented and tested.Comment: 22 pages, 22 figures, accepted by JINS

Analog CMOS Readout Channel for Time and Amplitude Measurements With Radiation Sensitivity Analysis for Gain-Boosting Amplifiers

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 μm x 290 μm . The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10–70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.Ministerio de Ciencia, Innovación y Universidades PGC2018-095640-B-I00Consejería de Transformación Económica, Industria, Conocimiento y Universidades P18-FR-3852 y P18-FR-431

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC

The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130 nm CMOS process, shows a performance of 67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5 ns (to first bit read out), while its total power consumption is 50 mW/channel. The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to single event effects during irradiation is measured and determined to meet the system requirements

A 10-bit 40MS/s Pipelined ADC in a 0.13μm CMOS Process

This paper presents a 10-bit analogue to digital converter (ADC) that will be integrated in a general purpose charge readout ASIC that is the new generation of mixed-mode integrated circuits for Time Projection Chamber (TPC) readout. It is based on a pipelined structure with double sampling and was implemented with switched capacitor circuits in eight 1.5-bit stages followed by a 2-bit stage. The power consumption is adjustable with the conversion rate and varies between 15 and 34mW for a 15 to 40MS/s conversion speed. The ADC occupies a silicon area of 0.7mm2 in a 0.13μm CMOS process and operates from a single 1.5V supply

Low Noise Pre-amplifier/Amplifier Chain for High Capacitance Sensors

In the past two decades, imaging sensors and detectors have developed tremendously. This technology has found its way into a number of areas, such as space missions, synchrotron light sources, and medical imaging. Nowadays, detectors and custom ICs are routine in high-energy physics applications. Electronic readout circuits have become a key part of every modern detector system. Many sensing circuits in detectors depend upon accumulating charge on a capacitor. The charge uncertainty on the capacitor when it is reset causes a signal error known as reset noise. Therefore, low noise readout circuitry capable of driving high input capacitance is essential for detector systems. A low noise pre-amplifier/amplifier readout circuitry has been designed and fabricated in 0.13um IBM CMOS8RF process technology. The pre-amplifier/ amplifier chain employs correlated double sampling at the input to suppress the kTC noise without any additional circuitry. In order to increase the signal-to-noise ratio, capacitive matching is used at the amplifier input. The experimental results of the signal processing chain employing capacitive matching and correlated double sampling show more than 60 times improvement in the signal-to-noise ratio over the same circuit without these improvements. In this dissertation a novel auto-zeroing technique is introduced as well. This technique uses a nulling point other than the amplifier's input and output to perform the auto-zeroing operation. The auto-zeroing is performed by taking advantage of emitter degeneration in the input transistor pair of the differential pair. For testing purposes this technique is implemented on a telescopic cascode differential amplifier. The auto-zeroed telescopic cascode differential amplifier has also been designed and fabricated in 0.13um IBM CMOS8RF process technology. This auto-zeroing technique reduces the input referred offset noise by an order of magnitude

Design, fabrication and calibration of alpha particle densitometers for measuring planetary atmospheric density

An alpha particle densitometer was developed for possible application to measurement of the atmospheric density-altitude profile on Martian entry. The device uses an Am-241 radioactive-foil source, which emits a distributed energy spectrum, located about 25 to 75 cm from a semiconductor detector. System response - defined as the number of alphas per second reaching the detector with energy above a fixed threshold - is given for Ar and CO2. The altitude profile of density measurement accuracy is given for a pure CO2 atmosphere with 5 mb surface pressure. The entire unit, including dc-dc converters, requires less than 350 milliwatts of power from +28 volts, weighs about 0.85 lb and occupies less than 15 cubic inches volume

Noise Efficient Integrated Amplifier Designs for Biomedical Applications

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√Hz with a 10 µA bias current, which results in a NEF of 1.2